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DSPCore: Make ifx registers private

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These aren't used externally, so they can be made private.
This commit is contained in:
Lioncash 2020-12-29 14:22:37 -05:00
parent e3de37e47b
commit 5fb1f0bfd3
3 changed files with 19 additions and 19 deletions
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2
Source/Core/Core/DSP/DSPCore.cpp
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@ -385,7 +385,7 @@ void SDSP::DoState(PointerWrap& p)
} }
p.Do(step_counter); p.Do(step_counter);
p.DoArray(ifx_regs); p.DoArray(m_ifx_regs);
m_accelerator->DoState(p); m_accelerator->DoState(p);
p.Do(m_mailbox[0]); p.Do(m_mailbox[0]);
p.Do(m_mailbox[1]); p.Do(m_mailbox[1]);

6
Source/Core/Core/DSP/DSPCore.h
View File

@ -429,9 +429,6 @@ struct SDSP
u32 iram_crc = 0; u32 iram_crc = 0;
u64 step_counter = 0; u64 step_counter = 0;
// Accelerator / DMA / other hardware registers. Not GPRs.
std::array<u16, 256> ifx_regs{};
// When state saving, all of the above can just be memcpy'd into the save state. // When state saving, all of the above can just be memcpy'd into the save state.
// The below needs special handling. // The below needs special handling.
u16* iram = nullptr; u16* iram = nullptr;
@ -453,6 +450,9 @@ private:
u16 ReadIFXImpl(u16 address); u16 ReadIFXImpl(u16 address);
// Accelerator / DMA / other hardware registers. Not GPRs.
std::array<u16, 256> m_ifx_regs{};
std::unique_ptr<Accelerator> m_accelerator; std::unique_ptr<Accelerator> m_accelerator;
std::array<std::atomic<u32>, 2> m_mailbox; std::array<std::atomic<u32>, 2> m_mailbox;
DSPCore& m_dsp_core; DSPCore& m_dsp_core;

30
Source/Core/Core/DSP/DSPHWInterface.cpp
View File

@ -23,7 +23,7 @@ namespace DSP
{ {
void SDSP::InitializeIFX() void SDSP::InitializeIFX()
{ {
ifx_regs.fill(0); m_ifx_regs.fill(0);
GetMailbox(Mailbox::CPU).store(0); GetMailbox(Mailbox::CPU).store(0);
GetMailbox(Mailbox::DSP).store(0); GetMailbox(Mailbox::DSP).store(0);
@ -118,14 +118,14 @@ void SDSP::WriteIFX(u32 address, u16 value)
break; break;
case DSP_DSBL: case DSP_DSBL:
ifx_regs[DSP_DSBL] = value; m_ifx_regs[DSP_DSBL] = value;
ifx_regs[DSP_DSCR] |= 4; // Doesn't really matter since we do DMA instantly m_ifx_regs[DSP_DSCR] |= 4; // Doesn't really matter since we do DMA instantly
if (!ifx_regs[DSP_AMDM]) if (!m_ifx_regs[DSP_AMDM])
DoDMA(); DoDMA();
else else
NOTICE_LOG_FMT(DSPLLE, "Masked DMA skipped"); NOTICE_LOG_FMT(DSPLLE, "Masked DMA skipped");
ifx_regs[DSP_DSCR] &= ~4; m_ifx_regs[DSP_DSCR] &= ~4;
ifx_regs[DSP_DSBL] = 0; m_ifx_regs[DSP_DSBL] = 0;
break; break;
case DSP_GAIN: case DSP_GAIN:
@ -138,7 +138,7 @@ void SDSP::WriteIFX(u32 address, u16 value)
case DSP_DSMAH: case DSP_DSMAH:
case DSP_DSMAL: case DSP_DSMAL:
case DSP_DSCR: case DSP_DSCR:
ifx_regs[address & 0xFF] = value; m_ifx_regs[address & 0xFF] = value;
break; break;
case DSP_ACSAH: case DSP_ACSAH:
@ -199,7 +199,7 @@ void SDSP::WriteIFX(u32 address, u16 value)
{ {
ERROR_LOG_FMT(DSPLLE, "{:04x} MW {:04x} ({:04x})", pc, address, value); ERROR_LOG_FMT(DSPLLE, "{:04x} MW {:04x} ({:04x})", pc, address, value);
} }
ifx_regs[address & 0xFF] = value; m_ifx_regs[address & 0xFF] = value;
break; break;
} }
} }
@ -221,7 +221,7 @@ u16 SDSP::ReadIFXImpl(u16 address)
return ReadMailboxLow(Mailbox::CPU); return ReadMailboxLow(Mailbox::CPU);
case DSP_DSCR: case DSP_DSCR:
return ifx_regs[address & 0xFF]; return m_ifx_regs[address & 0xFF];
case DSP_ACSAH: case DSP_ACSAH:
return static_cast<u16>(m_accelerator->GetStartAddress() >> 16); return static_cast<u16>(m_accelerator->GetStartAddress() >> 16);
@ -244,13 +244,13 @@ u16 SDSP::ReadIFXImpl(u16 address)
case DSP_PRED_SCALE: case DSP_PRED_SCALE:
return m_accelerator->GetPredScale(); return m_accelerator->GetPredScale();
case DSP_ACCELERATOR: // ADPCM Accelerator reads case DSP_ACCELERATOR: // ADPCM Accelerator reads
return m_accelerator->Read(reinterpret_cast<s16*>(&ifx_regs[DSP_COEF_A1_0])); return m_accelerator->Read(reinterpret_cast<s16*>(&m_ifx_regs[DSP_COEF_A1_0]));
case DSP_ACDATA1: // Accelerator reads (Zelda type) - "UnkZelda" case DSP_ACDATA1: // Accelerator reads (Zelda type) - "UnkZelda"
return m_accelerator->ReadD3(); return m_accelerator->ReadD3();
default: default:
{ {
const u16 ifx_reg = ifx_regs[address & 0xFF]; const u16 ifx_reg = m_ifx_regs[address & 0xFF];
if ((address & 0xff) >= 0xa0) if ((address & 0xff) >= 0xa0)
{ {
@ -323,10 +323,10 @@ const u8* SDSP::DDMAOut(u16 dsp_addr, u32 addr, u32 size)
void SDSP::DoDMA() void SDSP::DoDMA()
{ {
const u32 addr = (ifx_regs[DSP_DSMAH] << 16) | ifx_regs[DSP_DSMAL]; const u32 addr = (m_ifx_regs[DSP_DSMAH] << 16) | m_ifx_regs[DSP_DSMAL];
const u16 ctl = ifx_regs[DSP_DSCR]; const u16 ctl = m_ifx_regs[DSP_DSCR];
const u16 dsp_addr = ifx_regs[DSP_DSPA] * 2; const u16 dsp_addr = m_ifx_regs[DSP_DSPA] * 2;
const u16 len = ifx_regs[DSP_DSBL]; const u16 len = m_ifx_regs[DSP_DSBL];
if (len > 0x4000) if (len > 0x4000)
{ {