diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.h b/Source/Core/Core/PowerPC/JitArm64/Jit.h
index 35375f8302..bf266acfd3 100644
--- a/Source/Core/Core/PowerPC/JitArm64/Jit.h
+++ b/Source/Core/Core/PowerPC/JitArm64/Jit.h
@@ -253,7 +253,8 @@ protected:
   void GenerateConvertDoubleToSingle();
   void GenerateConvertSingleToDouble();
   void GenerateFPRF(bool single);
-  void GenerateQuantizedLoadStores();
+  void GenerateQuantizedLoads();
+  void GenerateQuantizedStores();
 
   // Profiling
   void BeginTimeProfile(JitBlock* b);
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
index 76d73edd50..da6af010d9 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
@@ -25,8 +25,8 @@ void JitArm64::psq_lXX(UGeckoInstruction inst)
   FALLBACK_IF(!MSR.DR);
 
   // X30 is LR
-  // X0 contains the scale
-  // X1 is the address
+  // X0 is the address
+  // X1 contains the scale
   // X2 is a temporary
   // Q0 is the return register
   // Q1 is a temporary
@@ -39,8 +39,8 @@ void JitArm64::psq_lXX(UGeckoInstruction inst)
   gpr.Lock(ARM64Reg::W0, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30);
   fpr.Lock(ARM64Reg::Q0, ARM64Reg::Q1);
 
-  constexpr ARM64Reg scale_reg = ARM64Reg::W0;
-  constexpr ARM64Reg addr_reg = ARM64Reg::W1;
+  constexpr ARM64Reg addr_reg = ARM64Reg::W0;
+  constexpr ARM64Reg scale_reg = ARM64Reg::W1;
   constexpr ARM64Reg type_reg = ARM64Reg::W2;
   ARM64Reg VS;
 
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
index fd415e8da2..40129ce202 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
@@ -223,7 +223,8 @@ void JitArm64::GenerateCommonAsm()
   GenerateFPRF(false);
   JitRegister::Register(GetAsmRoutines()->fprf_single, GetCodePtr(), "JIT_FPRF");
 
-  GenerateQuantizedLoadStores();
+  GenerateQuantizedLoads();
+  GenerateQuantizedStores();
 }
 
 // Input: X1 contains input, and D0 contains result of running the input through AArch64 FRECPE.
@@ -483,17 +484,15 @@ void JitArm64::GenerateFPRF(bool single)
   B(write_fprf_and_ret);
 }
 
-void JitArm64::GenerateQuantizedLoadStores()
+void JitArm64::GenerateQuantizedLoads()
 {
-  // X0 is the scale
-  // X1 is address
-  // X2 is a temporary on stores
+  // X0 is the address
+  // X1 is the scale
   // X30 is LR
-  // Q0 is the return for loads
-  //    is the register for stores
+  // Q0 is the return
   // Q1 is a temporary
-  ARM64Reg addr_reg = ARM64Reg::X1;
-  ARM64Reg scale_reg = ARM64Reg::X0;
+  ARM64Reg addr_reg = ARM64Reg::X0;
+  ARM64Reg scale_reg = ARM64Reg::X1;
   ARM64FloatEmitter float_emit(this);
 
   const u8* start = GetCodePtr();
@@ -652,9 +651,21 @@ void JitArm64::GenerateQuantizedLoadStores()
   single_load_quantized[5] = loadPairedU16One;
   single_load_quantized[6] = loadPairedS8One;
   single_load_quantized[7] = loadPairedS16One;
+}
 
-  // Stores
-  start = GetCodePtr();
+void JitArm64::GenerateQuantizedStores()
+{
+  // X0 is the scale
+  // X1 is the address
+  // X2 is a temporary
+  // X30 is LR
+  // Q0 is the register
+  // Q1 is a temporary
+  ARM64Reg scale_reg = ARM64Reg::X0;
+  ARM64Reg addr_reg = ARM64Reg::X1;
+  ARM64FloatEmitter float_emit(this);
+
+  const u8* start = GetCodePtr();
   const u8* storePairedIllegal = GetCodePtr();
   BRK(0x101);
   const u8* storePairedFloat;