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Merge pull request #2611 from Sonicadvance1/aarch64_fix_register_cache

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[AArch64] Fix a few bugs in the FPR cache.
This commit is contained in:
Ryan Houdek 2015-06-14 19:03:40 -05:00
commit 73d213142f
2 changed files with 15 additions and 18 deletions
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1
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
View File

@ -21,7 +21,6 @@ void JitArm64::psq_l(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStorePairedOff); JITDISABLE(bJITLoadStorePairedOff);
FALLBACK_IF(jo.memcheck || !jo.fastmem); FALLBACK_IF(jo.memcheck || !jo.fastmem);
FALLBACK_IF(true);
// X30 is LR // X30 is LR
// X0 contains the scale // X0 contains the scale

30
Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp
View File

@ -261,21 +261,10 @@ void Arm64FPRCache::Flush(FlushMode mode, PPCAnalyst::CodeOp* op)
{ {
for (int i = 0; i < 32; ++i) for (int i = 0; i < 32; ++i)
{ {
bool flush = true;
if (mode == FLUSH_INTERPRETER)
{
if (!(op->regsOut[i] || op->regsIn[i]))
{
// This interpreted instruction doesn't use this register
flush = false;
}
}
if (m_guest_registers[i].GetType() == REG_REG) if (m_guest_registers[i].GetType() == REG_REG)
{ {
// Has to be flushed if it isn't in a callee saved register // XXX: Determine if we can keep a register in the lower 64bits
ARM64Reg host_reg = m_guest_registers[i].GetReg(); // Which will allow it to be callee saved.
if (flush || !IsCalleeSaved(host_reg))
FlushRegister(i, mode == FLUSH_MAINTAIN_STATE); FlushRegister(i, mode == FLUSH_MAINTAIN_STATE);
} }
} }
@ -342,7 +331,16 @@ void Arm64FPRCache::GetAllocationOrder()
void Arm64FPRCache::FlushByHost(ARM64Reg host_reg) void Arm64FPRCache::FlushByHost(ARM64Reg host_reg)
{ {
// XXX: Scan guest registers and flush if found for (int i = 0; i < 32; ++i)
{
OpArg& reg = m_guest_registers[i];
if (reg.GetType() == REG_REG && reg.GetReg() == host_reg)
{
FlushRegister(i, false);
return;
}
}
} }
bool Arm64FPRCache::IsCalleeSaved(ARM64Reg reg) bool Arm64FPRCache::IsCalleeSaved(ARM64Reg reg)
@ -351,7 +349,7 @@ bool Arm64FPRCache::IsCalleeSaved(ARM64Reg reg)
{ {
Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, INVALID_REG, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, INVALID_REG,
}; };
return std::find(callee_regs.begin(), callee_regs.end(), EncodeRegTo64(reg)) != callee_regs.end(); return std::find(callee_regs.begin(), callee_regs.end(), reg) != callee_regs.end();
} }
void Arm64FPRCache::FlushRegister(u32 preg, bool maintain_state) void Arm64FPRCache::FlushRegister(u32 preg, bool maintain_state)
@ -377,6 +375,6 @@ BitSet32 Arm64FPRCache::GetCallerSavedUsed()
BitSet32 registers(0); BitSet32 registers(0);
for (auto& it : m_host_registers) for (auto& it : m_host_registers)
if (it.IsLocked()) if (it.IsLocked())
registers[Q0 - it.GetReg()] = 1; registers[it.GetReg() - Q0] = 1;
return registers; return registers;
} }