From 7b9d0dbedc5c9d8c94d8a300eec6af8358d1cb27 Mon Sep 17 00:00:00 2001 From: nodchip Date: Thu, 19 Aug 2010 14:10:22 +0000 Subject: [PATCH] JitIL: Added some instruction handlers. They were ported from Jit64. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6110 8ced0084-cf51-0410-be5f-012b33b47a6e --- Source/Core/Core/Src/PowerPC/Jit64IL/IR.h | 3 + Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.h | 4 +- .../Src/PowerPC/Jit64IL/JitIL_Integer.cpp | 68 ++++++++++++------- .../Core/Src/PowerPC/Jit64IL/JitIL_Tables.cpp | 16 ++--- 4 files changed, 54 insertions(+), 37 deletions(-) diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/IR.h b/Source/Core/Core/Src/PowerPC/Jit64IL/IR.h index d143b3ad4b..28b1e3452e 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64IL/IR.h +++ b/Source/Core/Core/Src/PowerPC/Jit64IL/IR.h @@ -286,6 +286,9 @@ public: InstLoc EmitStoreGReg(InstLoc value, unsigned reg) { return FoldUOp(StoreGReg, value, reg); } + InstLoc EmitNot(InstLoc op1) { + return EmitXor(op1, EmitIntConst(-1U)); + } InstLoc EmitAnd(InstLoc op1, InstLoc op2) { return FoldBiOp(And, op1, op2); } diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.h b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.h index 23a4c196f0..cabbec990b 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.h +++ b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.h @@ -140,9 +140,7 @@ public: void DynaRunTable63(UGeckoInstruction _inst); void addx(UGeckoInstruction inst); - void orx(UGeckoInstruction inst); - void xorx(UGeckoInstruction inst); - void andx(UGeckoInstruction inst); + void boolX(UGeckoInstruction inst); void mulli(UGeckoInstruction inst); void mulhwux(UGeckoInstruction inst); void mullwx(UGeckoInstruction inst); diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_Integer.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_Integer.cpp index 3623b06551..a2041c35b5 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_Integer.cpp +++ b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_Integer.cpp @@ -130,39 +130,55 @@ void JitIL::cmpXX(UGeckoInstruction inst) ibuild.EmitStoreCR(res, inst.CRFD); } -void JitIL::orx(UGeckoInstruction inst) +void JitIL::boolX(UGeckoInstruction inst) { INSTRUCTION_START JITDISABLE(Integer) - IREmitter::InstLoc val = ibuild.EmitLoadGReg(inst.RB); - val = ibuild.EmitOr(ibuild.EmitLoadGReg(inst.RS), val); - ibuild.EmitStoreGReg(val, inst.RA); - if (inst.Rc) - ComputeRC(ibuild, val); -} + IREmitter::InstLoc a = NULL; + IREmitter::InstLoc s = ibuild.EmitLoadGReg(inst.RS); + IREmitter::InstLoc b = ibuild.EmitLoadGReg(inst.RB); -// m_GPR[_inst.RA] = m_GPR[_inst.RS] ^ m_GPR[_inst.RB]; -void JitIL::xorx(UGeckoInstruction inst) -{ - INSTRUCTION_START - JITDISABLE(Integer) - IREmitter::InstLoc val = ibuild.EmitLoadGReg(inst.RB); - val = ibuild.EmitXor(ibuild.EmitLoadGReg(inst.RS), val); - ibuild.EmitStoreGReg(val, inst.RA); - if (inst.Rc) - ComputeRC(ibuild, val); -} + if (inst.SUBOP10 == 28) /* andx */ + { + a = ibuild.EmitAnd(s, b); + } + else if (inst.SUBOP10 == 476) /* nandx */ + { + a = ibuild.EmitNot(ibuild.EmitAnd(s, b)); + } + else if (inst.SUBOP10 == 60) /* andcx */ + { + a = ibuild.EmitAnd(s, ibuild.EmitNot(b)); + } + else if (inst.SUBOP10 == 444) /* orx */ + { + a = ibuild.EmitOr(s, b); + } + else if (inst.SUBOP10 == 124) /* norx */ + { + a = ibuild.EmitNot(ibuild.EmitOr(s, b)); + } + else if (inst.SUBOP10 == 412) /* orcx */ + { + a = ibuild.EmitOr(s, ibuild.EmitNot(b)); + } + else if (inst.SUBOP10 == 316) /* xorx */ + { + a = ibuild.EmitXor(s, b); + } + else if (inst.SUBOP10 == 284) /* eqvx */ + { + a = ibuild.EmitNot(ibuild.EmitXor(s, b)); + } + else + { + PanicAlert("WTF!"); + } -void JitIL::andx(UGeckoInstruction inst) -{ - INSTRUCTION_START - JITDISABLE(Integer) - IREmitter::InstLoc val = ibuild.EmitLoadGReg(inst.RB); - val = ibuild.EmitAnd(ibuild.EmitLoadGReg(inst.RS), val); - ibuild.EmitStoreGReg(val, inst.RA); + ibuild.EmitStoreGReg(a, inst.RA); if (inst.Rc) - ComputeRC(ibuild, val); + ComputeRC(ibuild, a); } void JitIL::extsbx(UGeckoInstruction inst) diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_Tables.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_Tables.cpp index 8de8ae08e5..6830f9da1d 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_Tables.cpp +++ b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_Tables.cpp @@ -195,14 +195,14 @@ static GekkoOPTemplate table19[] = static GekkoOPTemplate table31[] = { - {28, &JitIL::andx}, //"andx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, - {60, &JitIL::Default}, //"andcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, - {444, &JitIL::orx}, //"orx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, - {124, &JitIL::Default}, //"norx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, - {316, &JitIL::xorx}, //"xorx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, - {412, &JitIL::Default}, //"orcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, - {476, &JitIL::Default}, //"nandx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, - {284, &JitIL::Default}, //"eqvx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {28, &JitIL::boolX}, //"andx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {60, &JitIL::boolX}, //"andcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {444, &JitIL::boolX}, //"orx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {124, &JitIL::boolX}, //"norx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {316, &JitIL::boolX}, //"xorx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {412, &JitIL::boolX}, //"orcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {476, &JitIL::boolX}, //"nandx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {284, &JitIL::boolX}, //"eqvx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {0, &JitIL::cmpXX}, //"cmp", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}}, {32, &JitIL::cmpXX}, //"cmpl", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}}, {26, &JitIL::cntlzwx}, //"cntlzwx",OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},