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Merge pull request #9851 from JosJuice/jitarm64-mfcr
JitArm64: Handle SO and LT simultaneously in mfcr
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commit
856c82aa24
@ -613,6 +613,7 @@ void JitArm64::mfcr(UGeckoInstruction inst)
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gpr.BindToRegister(inst.RD, false);
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gpr.BindToRegister(inst.RD, false);
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ARM64Reg WA = gpr.R(inst.RD);
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ARM64Reg WA = gpr.R(inst.RD);
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ARM64Reg WB = gpr.GetReg();
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ARM64Reg WC = gpr.GetReg();
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ARM64Reg WC = gpr.GetReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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ARM64Reg XA = EncodeRegTo64(WA);
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ARM64Reg XC = EncodeRegTo64(WC);
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ARM64Reg XC = EncodeRegTo64(WC);
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@ -622,33 +623,34 @@ void JitArm64::mfcr(UGeckoInstruction inst)
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ARM64Reg CR = gpr.CR(i);
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ARM64Reg CR = gpr.CR(i);
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ARM64Reg WCR = EncodeRegTo32(CR);
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ARM64Reg WCR = EncodeRegTo32(CR);
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// SO
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// SO and LT
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static_assert(PowerPC::CR_SO_BIT == 0);
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static_assert(PowerPC::CR_LT_BIT == 3);
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static_assert(PowerPC::CR_EMU_LT_BIT - PowerPC::CR_EMU_SO_BIT == 3);
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UBFX(XC, CR, PowerPC::CR_EMU_SO_BIT, 4);
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if (i == 0)
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if (i == 0)
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{
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{
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UBFX(XA, CR, PowerPC::CR_EMU_SO_BIT, 1);
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MOVI2R(WB, PowerPC::CR_SO | PowerPC::CR_LT);
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AND(WA, WC, WB);
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}
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}
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else
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else
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{
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{
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UBFX(XC, CR, PowerPC::CR_EMU_SO_BIT, 1);
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AND(WC, WC, WB);
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ORR(XA, XC, XA, ArithOption(XA, ShiftType::LSL, 4));
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ORR(XA, XC, XA, ArithOption(XA, ShiftType::LSL, 4));
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}
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}
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// EQ
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// EQ
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ORR(WC, WA, 32 - 1, 0); // WA | 1<<1
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ORR(WC, WA, 32 - PowerPC::CR_EQ_BIT, 0);
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CMP(WCR, ARM64Reg::WZR);
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CMP(WCR, ARM64Reg::WZR);
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CSEL(WA, WC, WA, CC_EQ);
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CSEL(WA, WC, WA, CC_EQ);
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// GT
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// GT
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ORR(WC, WA, 32 - 2, 0); // WA | 1<<2
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ORR(WC, WA, 32 - PowerPC::CR_GT_BIT, 0);
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CMP(CR, ARM64Reg::ZR);
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CMP(CR, ARM64Reg::ZR);
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CSEL(WA, WC, WA, CC_GT);
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CSEL(WA, WC, WA, CC_GT);
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// LT
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UBFX(XC, CR, PowerPC::CR_EMU_LT_BIT, 1);
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ORR(WA, WA, WC, ArithOption(WC, ShiftType::LSL, 3));
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}
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}
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gpr.Unlock(WC);
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gpr.Unlock(WB, WC);
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}
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}
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void JitArm64::mtcrf(UGeckoInstruction inst)
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void JitArm64::mtcrf(UGeckoInstruction inst)
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