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[ARM] Reenable flush per instruction with FPR cache. Something is still very wrong.

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Ryan Houdek 2013-09-19 02:08:10 +00:00
parent 930f997f04
commit 85f067780a
1 changed files with 1 additions and 0 deletions
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Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp
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@ -483,6 +483,7 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
BKPT(0x7777); BKPT(0x7777);
} }
JitArmTables::CompileInstruction(ops[i]); JitArmTables::CompileInstruction(ops[i]);
fpr.Flush();
if (js.memcheck && (opinfo->flags & FL_LOADSTORE)) if (js.memcheck && (opinfo->flags & FL_LOADSTORE))
{ {
// Don't do this yet // Don't do this yet