From 89178f411cf1e8ef61b005197545618e53a0d4e8 Mon Sep 17 00:00:00 2001 From: nakeee Date: Wed, 22 Apr 2009 19:08:13 +0000 Subject: [PATCH] DSP switched mode 16 and 40 git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3045 8ced0084-cf51-0410-be5f-012b33b47a6e --- Source/Core/Common/Src/SDCardUtil.cpp | 2 +- Source/Core/DSPCore/Src/DSPInterpreter.cpp | 10 +++++----- Source/Core/DSPCore/Src/DSPTables.cpp | 8 +++----- Source/Core/DSPCore/Src/gdsp_registers.h | 21 ++++++++++++--------- Source/DSPSpy/dsp_code.ds | 12 ++++++------ 5 files changed, 27 insertions(+), 26 deletions(-) diff --git a/Source/Core/Common/Src/SDCardUtil.cpp b/Source/Core/Common/Src/SDCardUtil.cpp index 96f368d7e5..1638ede08c 100644 --- a/Source/Core/Common/Src/SDCardUtil.cpp +++ b/Source/Core/Common/Src/SDCardUtil.cpp @@ -192,7 +192,7 @@ bool SDCardCreate(u32 disk_size /*in MB*/, char* filename) // Convert MB to bytes disk_size *= 1024*1024; - if (disk_size < 0x800000 || disk_size > 0x800000000) + if (disk_size < 0x800000 || disk_size > 0x800000000ULL) ERROR_LOG(COMMON, "Trying to create SD Card image of size %iMB is out of range (8MB-32GB)", disk_size/(1024*1024)); sectors_per_disk = disk_size / 512; diff --git a/Source/Core/DSPCore/Src/DSPInterpreter.cpp b/Source/Core/DSPCore/Src/DSPInterpreter.cpp index b7e0162cbb..774da08cbb 100644 --- a/Source/Core/DSPCore/Src/DSPInterpreter.cpp +++ b/Source/Core/DSPCore/Src/DSPInterpreter.cpp @@ -1468,7 +1468,7 @@ void srbith(const UDSPInstruction& opc) // 15-bit precision? clamping? no idea :( // CLR15 seems to be the default. - // nakee: It seems to come around mul operation, and it explains what sets the mul bit. But if so why not set/clr14? + // It seems to come around mul operation, case 0xc: // CLR15 g_dsp.r[DSP_REG_SR] &= ~SR_TOP_BIT_UNK; break; @@ -1479,12 +1479,12 @@ void srbith(const UDSPInstruction& opc) // 40-bit precision? clamping? no idea :( // 40 seems to be the default. // Confirmed these by using DSPSpy and copying the value of SR to R00 after setting. - case 0xe: // SET40 (really, clear SR's 0x4000) something about "set 40-bit operation"? - g_dsp.r[DSP_REG_SR] &= ~SR_16_BIT; + case 0xe: // SET16 (really, clear SR's 0x4000) + g_dsp.r[DSP_REG_SR] &= ~SR_40_MODE_BIT; break; - case 0xf: // SET16 (really, set SR's 0x4000) something about "set 16-bit operation"? - g_dsp.r[DSP_REG_SR] |= SR_16_BIT; + case 0xf: // SET40 (really, set SR's 0x4000) + g_dsp.r[DSP_REG_SR] |= SR_40_MODE_BIT; break; default: diff --git a/Source/Core/DSPCore/Src/DSPTables.cpp b/Source/Core/DSPCore/Src/DSPTables.cpp index 321b253718..40aac6792d 100644 --- a/Source/Core/DSPCore/Src/DSPTables.cpp +++ b/Source/Core/DSPCore/Src/DSPTables.cpp @@ -218,13 +218,11 @@ const DSPOPCTemplate opcodes[] = {"M2", 0x8a00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"M0", 0x8b00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, - // These guys probably change the precision or range of some operations. - // calculations or something? Or clamp? - // SET15/CLR15 is commonly used around MULXAC in Zeldas. {"CLR15", 0x8c00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"SET15", 0x8d00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, - {"SET40", 0x8e00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, - {"SET16", 0x8f00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, + + {"SET16", 0x8e00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, + {"SET40", 0x8f00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"INCM", 0x7400, 0xfeff, DSPInterpreter::incm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, diff --git a/Source/Core/DSPCore/Src/gdsp_registers.h b/Source/Core/DSPCore/Src/gdsp_registers.h index 9e04a77705..961b03872a 100644 --- a/Source/Core/DSPCore/Src/gdsp_registers.h +++ b/Source/Core/DSPCore/Src/gdsp_registers.h @@ -93,15 +93,18 @@ #define DSP_STACK_D 1 -#define SR_UNKNOWN 0x0002 // ???????? -#define SR_ARITH_ZERO 0x0004 -#define SR_SIGN 0x0008 // tested -#define SR_TOP2BITS 0x0020 // this is an odd one. -#define SR_LOGIC_ZERO 0x0040 -#define SR_INT_ENABLE 0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so. -#define SR_MUL_MODIFY 0x2000 // 1 = normal. 0 = x2 (M0, M2) -#define SR_TOP_BIT_UNK 0x8000 // 1 = normal. 0 = x2 (CLR15, SET15) -#define SR_16_BIT 0x4000 // 1 = "16", 0 = "40" (SET40, SET16) .. actually, seems it's the reverse. Controls sign extension when loading mid accums. +// SR bits +#define SR_CARRY 0x0001 +#define SR_UNKNOWN 0x0002 // ???????? +#define SR_ARITH_ZERO 0x0004 +#define SR_SIGN 0x0008 +#define SR_TOP2BITS 0x0020 // this is an odd one. +#define SR_LOGIC_ZERO 0x0040 +#define SR_INT_ENABLE 0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so. +#define SR_MUL_MODIFY 0x2000 // 1 = normal. 0 = x2 (M0, M2) +#define SR_40_MODE_BIT 0x4000 // 0 = "16", 1 = "40" (SET16, SET40) Controls sign extension when loading mid accums. +#define SR_TOP_BIT_UNK 0x8000 // 1 = normal. 0 = x2 (CLR15, SET15) ???????? + void dsp_reg_store_stack(u8 stack_reg, u16 val); u16 dsp_reg_load_stack(u8 stack_reg); diff --git a/Source/DSPSpy/dsp_code.ds b/Source/DSPSpy/dsp_code.ds index 9808736332..5f9d2d92cc 100644 --- a/Source/DSPSpy/dsp_code.ds +++ b/Source/DSPSpy/dsp_code.ds @@ -180,8 +180,8 @@ main: ; We can call send_back at any time to send data back to the PowerPC. -; Calling set16 here seemed to crash the dsp tester in strange ways -; until I added set40 in send_back. Seems clear that it affects something important. +; Calling set40 here seemed to crash the dsp tester in strange ways +; until I added set16 in send_back. Seems clear that it affects something important. nop nop @@ -539,7 +539,7 @@ irq: ; it must write the contents of all regs to DRAM. send_back: ; make state safe. - set40 + set16 ; store registers to reg table sr @REGS_BASE, $r00 lri $r00, #(REGS_BASE + 1) @@ -646,10 +646,10 @@ dma_copy: ; If you are in s16 mode, use this instead of send_back if you want to stay ; in s16 mode. -send_back_16: - set40 - call send_back +send_back_40: set16 + call send_back + set40 ret ; This one's odd. Doesn't look like it should work since it uses acl0 but