Jit64: Recompile asm routines on cache clear

This is needed so that the checks added in the previous commit will be
reevaluated if the value of m_enable_dcache changes.

JitArm64 was already recompiling its asm routines on cache clear by
necessity. It doesn't have the same setup as Jit64 where the asm
routines are in a separate region, so clearing the JitArm64 cache
results in the asm routines being cleared too.
This commit is contained in:
JosJuice 2023-09-30 17:32:51 +02:00
parent 5e74a8b850
commit 899d61bc7d
6 changed files with 21 additions and 6 deletions

View File

@ -82,9 +82,14 @@ public:
} }
bool IsInSpace(const u8* ptr) const { return ptr >= region && ptr < (region + region_size); } bool IsInSpace(const u8* ptr) const { return ptr >= region && ptr < (region + region_size); }
// Cannot currently be undone. Will write protect the entire code region. void WriteProtect(bool allow_execute)
// Start over if you need to change the code (call FreeCodeSpace(), AllocCodeSpace()). {
void WriteProtect() { Common::WriteProtectMemory(region, region_size, true); } Common::WriteProtectMemory(region, region_size, allow_execute);
}
void UnWriteProtect(bool allow_execute)
{
Common::UnWriteProtectMemory(region, region_size, allow_execute);
}
void ResetCodePtr() { T::SetCodePtr(region, region + region_size); } void ResetCodePtr() { T::SetCodePtr(region, region + region_size); }
size_t GetSpaceLeft() const size_t GetSpaceLeft() const
{ {

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@ -305,6 +305,7 @@ void Jit64::ClearCache()
ClearCodeSpace(); ClearCodeSpace();
Clear(); Clear();
RefreshConfig(InitFastmemArena::No); RefreshConfig(InitFastmemArena::No);
asm_routines.Regenerate();
ResetFreeMemoryRanges(); ResetFreeMemoryRanges();
} }

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@ -32,7 +32,15 @@ void Jit64AsmRoutineManager::Init()
{ {
m_const_pool.Init(AllocChildCodeSpace(4096), 4096); m_const_pool.Init(AllocChildCodeSpace(4096), 4096);
Generate(); Generate();
WriteProtect(); WriteProtect(true);
}
void Jit64AsmRoutineManager::Regenerate()
{
UnWriteProtect(false);
ResetCodePtr();
Generate();
WriteProtect(true);
} }
// PLAN: no more block numbers - crazy opcodes just contain offset within // PLAN: no more block numbers - crazy opcodes just contain offset within

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@ -35,6 +35,7 @@ public:
explicit Jit64AsmRoutineManager(Jit64& jit); explicit Jit64AsmRoutineManager(Jit64& jit);
void Init(); void Init();
void Regenerate();
void ResetStack(Gen::X64CodeBlock& emitter); void ResetStack(Gen::X64CodeBlock& emitter);

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@ -56,7 +56,7 @@ VertexLoaderARM64::VertexLoaderARM64(const TVtxDesc& vtx_desc, const VAT& vtx_at
const Common::ScopedJITPageWriteAndNoExecute enable_jit_page_writes; const Common::ScopedJITPageWriteAndNoExecute enable_jit_page_writes;
ClearCodeSpace(); ClearCodeSpace();
GenerateVertexLoader(); GenerateVertexLoader();
WriteProtect(); WriteProtect(true);
} }
// Returns the register to use as the base and an offset from that register. // Returns the register to use as the base and an offset from that register.

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@ -49,7 +49,7 @@ VertexLoaderX64::VertexLoaderX64(const TVtxDesc& vtx_desc, const VAT& vtx_att)
AllocCodeSpace(4096); AllocCodeSpace(4096);
ClearCodeSpace(); ClearCodeSpace();
GenerateVertexLoader(); GenerateVertexLoader();
WriteProtect(); WriteProtect(true);
Common::JitRegister::Register(region, GetCodePtr(), "VertexLoaderX64\nVtx desc: \n{}\nVAT:\n{}", Common::JitRegister::Register(region, GetCodePtr(), "VertexLoaderX64\nVtx desc: \n{}\nVAT:\n{}",
vtx_desc, vtx_att); vtx_desc, vtx_att);