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Jit_LoadStore: stmw

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This commit is contained in:
MerryMage 2018-10-15 21:01:40 +01:00
parent 98cf0b3286
commit 9438ea0ef5
1 changed files with 14 additions and 13 deletions
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27
Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp
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@ -533,26 +533,27 @@ void Jit64::stmw(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff); JITDISABLE(bJITLoadStoreOff);
int a = inst.RA, d = inst.RD;
// TODO: This doesn't handle rollback on DSI correctly // TODO: This doesn't handle rollback on DSI correctly
for (int i = inst.RD; i < 32; i++) for (int i = d; i < 32; i++)
{ {
if (inst.RA) RCOpArg Ra = a ? gpr.Use(a, RCMode::Read) : RCOpArg::Imm32(0);
MOV(32, R(RSCRATCH), gpr.R(inst.RA)); RCOpArg Ri = gpr.Use(i, RCMode::Read);
else RegCache::Realize(Ra, Ri);
if (Ra.IsZero())
XOR(32, R(RSCRATCH), R(RSCRATCH)); XOR(32, R(RSCRATCH), R(RSCRATCH));
if (gpr.R(i).IsImm())
{
SafeWriteRegToReg(gpr.R(i), RSCRATCH, 32, (i - inst.RD) * 4 + (u32)(s32)inst.SIMM_16,
CallerSavedRegistersInUse());
}
else else
MOV(32, R(RSCRATCH), Ra);
if (!Ri.IsImm())
{ {
MOV(32, R(RSCRATCH2), gpr.R(i)); MOV(32, R(RSCRATCH2), Ri);
SafeWriteRegToReg(RSCRATCH2, RSCRATCH, 32, (i - inst.RD) * 4 + (u32)(s32)inst.SIMM_16, Ri = RCOpArg::R(RSCRATCH2);
CallerSavedRegistersInUse());
} }
SafeWriteRegToReg(Ri, RSCRATCH, 32, (i - d) * 4 + (u32)(s32)inst.SIMM_16,
CallerSavedRegistersInUse());
} }
gpr.UnlockAllX();
} }
void Jit64::eieio(UGeckoInstruction inst) void Jit64::eieio(UGeckoInstruction inst)