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Jit_LoadStore: lmw

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This commit is contained in:
MerryMage 2018-10-15 21:01:39 +01:00
parent c6b9712ac4
commit 98cf0b3286
1 changed files with 13 additions and 9 deletions
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22
Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp
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@ -510,18 +510,22 @@ void Jit64::lmw(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff); JITDISABLE(bJITLoadStoreOff);
int a = inst.RA, d = inst.RD;
// TODO: This doesn't handle rollback on DSI correctly // TODO: This doesn't handle rollback on DSI correctly
MOV(32, R(RSCRATCH2), Imm32((u32)(s32)inst.SIMM_16));
if (inst.RA)
ADD(32, R(RSCRATCH2), gpr.R(inst.RA));
for (int i = inst.RD; i < 32; i++)
{ {
SafeLoadToReg(RSCRATCH, R(RSCRATCH2), 32, (i - inst.RD) * 4, RCOpArg Ra = a ? gpr.Use(a, RCMode::Read) : RCOpArg::Imm32(0);
CallerSavedRegistersInUse() | BitSet32{RSCRATCH2}, false); RegCache::Realize(Ra);
gpr.BindToRegister(i, false, true); MOV_sum(32, RSCRATCH2, Ra, Imm32((u32)(s32)inst.SIMM_16));
MOV(32, gpr.R(i), R(RSCRATCH)); }
for (int i = d; i < 32; i++)
{
SafeLoadToReg(RSCRATCH, R(RSCRATCH2), 32, (i - d) * 4,
CallerSavedRegistersInUse() | BitSet32{RSCRATCH2}, false);
RCOpArg Ri = gpr.Bind(i, RCMode::Write);
RegCache::Realize(Ri);
MOV(32, Ri, R(RSCRATCH));
} }
gpr.UnlockAllX();
} }
void Jit64::stmw(UGeckoInstruction inst) void Jit64::stmw(UGeckoInstruction inst)