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DSPLLE: Implement conditional variants of RTI
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Pokechu22
parent
f9e36bfa67
commit
9b1d370478
@ -18,7 +18,7 @@
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namespace DSP
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{
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// clang-format off
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const std::array<DSPOPCTemplate, 215> s_opcodes =
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const std::array<DSPOPCTemplate, 230> s_opcodes =
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{{
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// # of parameters----+ {type, size, loc, lshift, mask} branch reads PC // instruction approximation
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// name opcode mask size-V V param 1 param 2 param 3 extendable uncond. updates SR
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@ -48,7 +48,22 @@ const std::array<DSPOPCTemplate, 215> s_opcodes =
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{"RETO", 0x02de, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if overflow
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{"RET", 0x02df, 0xffff, 1, 0, {}, false, true, true, false, false}, // unconditional return
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{"RTI", 0x02ff, 0xffff, 1, 0, {}, false, true, true, false, false}, // return from interrupt
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{"RTIGE", 0x02f0, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if greater or equal
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{"RTIL", 0x02f1, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if less
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{"RTIG", 0x02f2, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if greater
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{"RTILE", 0x02f3, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if less or equal
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{"RTINZ", 0x02f4, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if not zero
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{"RTIZ", 0x02f5, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if zero
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{"RTINC", 0x02f6, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if not carry
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{"RTIC", 0x02f7, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if carry
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{"RTIx8", 0x02f8, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if TODO
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{"RTIx9", 0x02f9, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if TODO
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{"RTIxA", 0x02fa, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if TODO
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{"RTIxB", 0x02fb, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if TODO
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{"RTILNZ", 0x02fc, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if logic not zero
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{"RTILZ", 0x02fd, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if logic zero
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{"RTIO", 0x02fe, 0xffff, 1, 0, {}, false, true, false, true, false}, // return from interrupt if overflow
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{"RTI", 0x02ff, 0xffff, 1, 0, {}, false, true, true, false, false}, // return from interrupt unconditionally
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{"CALLGE", 0x02b0, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if greater or equal
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{"CALLL", 0x02b1, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if less
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@ -104,13 +104,17 @@ void Interpreter::ret(const UDSPInstruction opc)
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state.pc = state.PopStack(StackRegister::Call);
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}
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// RTI
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// RTIcc
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// 0000 0010 1111 1111
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// Return from exception. Pops stored status register $sr from data stack
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// $st1 and program counter PC from call stack $st0 and sets $pc to this
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// location.
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void Interpreter::rti(const UDSPInstruction)
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// This instruction has a conditional form, but it is not used by any official ucode.
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void Interpreter::rti(const UDSPInstruction opc)
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{
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if (!CheckCondition(opc & 0xf))
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return;
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auto& state = m_dsp_core.DSPState();
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state.r.sr = state.PopStack(StackRegister::Data);
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state.pc = state.PopStack(StackRegister::Call);
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@ -32,7 +32,7 @@ constexpr std::array<InterpreterOpInfo, 125> s_opcodes
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{0x02d0, 0xfff0, &Interpreter::ret},
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{0x02ff, 0xffff, &Interpreter::rti},
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{0x02f0, 0xfff0, &Interpreter::rti},
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{0x02b0, 0xfff0, &Interpreter::call},
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@ -221,6 +221,7 @@ private:
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void r_callr(UDSPInstruction opc);
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void r_ifcc(UDSPInstruction opc);
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void r_ret(UDSPInstruction opc);
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void r_rti(UDSPInstruction opc);
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void Update_SR_Register(Gen::X64Reg val = Gen::EAX, Gen::X64Reg scratch = Gen::EDX);
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@ -255,12 +255,7 @@ void DSPEmitter::ret(const UDSPInstruction opc)
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ReJitConditional(opc, &DSPEmitter::r_ret);
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}
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// RTI
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// 0000 0010 1111 1111
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// Return from exception. Pops stored status register $sr from data stack
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// $st1 and program counter PC from call stack $st0 and sets $pc to this
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// location.
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void DSPEmitter::rti(const UDSPInstruction opc)
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void DSPEmitter::r_rti(const UDSPInstruction opc)
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{
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// g_dsp.r[DSP_REG_SR] = dsp_reg_load_stack(StackRegister::Data);
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dsp_reg_load_stack(StackRegister::Data);
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@ -268,6 +263,20 @@ void DSPEmitter::rti(const UDSPInstruction opc)
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// g_dsp.pc = dsp_reg_load_stack(StackRegister::Call);
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dsp_reg_load_stack(StackRegister::Call);
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MOV(16, M_SDSP_pc(), R(DX));
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WriteBranchExit();
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}
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// RTIcc
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// 0000 0010 1111 1111
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// Return from exception. Pops stored status register $sr from data stack
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// $st1 and program counter PC from call stack $st0 and sets $pc to this
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// location.
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// This instruction has a conditional form, but it is not used by any official ucode.
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// NOTE: Cannot use FallBackToInterpreter(opc) here because of the need to write branch exit
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void DSPEmitter::rti(const UDSPInstruction opc)
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{
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MOV(16, M_SDSP_pc(), Imm16(m_compile_pc + 1));
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ReJitConditional(opc, &DSPEmitter::r_rti);
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}
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// HALT
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@ -32,7 +32,7 @@ const std::array<JITOpInfo, 125> s_opcodes =
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{0x02d0, 0xfff0, &DSPEmitter::ret},
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{0x02ff, 0xffff, &DSPEmitter::rti},
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{0x02f0, 0xfff0, &DSPEmitter::rti},
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{0x02b0, 0xfff0, &DSPEmitter::call},
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55
Source/DSPSpy/tests/rti_test.ds
Normal file
55
Source/DSPSpy/tests/rti_test.ds
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@ -0,0 +1,55 @@
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; This test needs to manually specify IRQs
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jmp irq0
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jmp irq1
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jmp irq2
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jmp irq3
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jmp irq4
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jmp accov_irq
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jmp irq6
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jmp irq7
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incdir "tests"
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include "dsp_base_noirq.inc"
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test_main:
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; Use the accelerator to generate an IRQ by setting the start and end address to 0
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; This will result in an interrupt on every read
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SI @0xffda, #0 ; pred_scale
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SI @0xffdb, #0 ; yn1
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SI @0xffdc, #0 ; yn2
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SI @0xffd1, #0 ; SampleFormat
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SI @ACSAH, #0
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SI @ACCAH, #0
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SI @ACSAL, #0
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SI @ACCAL, #0
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SI @ACEAH, #0
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SI @ACEAL, #0
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LRI $AX1.H, #0x0000
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LRS $AX0.L, @ARAM ; Trigger interrupt
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CALL send_back
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LRI $AX1.H, #0x0001
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LRS $AX0.L, @ARAM ; Trigger interrupt
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CALL send_back
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LRI $AX1.H, #0x0000
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LRS $AX0.L, @ARAM ; Trigger interrupt
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CALL send_back
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jmp end_of_test
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accov_irq:
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; Restore registers, otherwise no new interrupt will be generated
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SI @0xffda, #0 ; pred_scale
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SI @0xffdb, #0 ; yn1
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SI @0xffdc, #0 ; yn2
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TSTAXH $AX1.H
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LRI $AX1.L, #0x1111
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cw 0x02f4 ; RTINZ if it exists
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LRI $AX1.L, #0x2222
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cw 0x02f5 ; RTIZ if it exists
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LRI $AX1.L, #0x3333
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RTI
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