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DSPHWInterface: Use an enum for indicating mailbox type
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5464e698fc
commit
9c73d63d40
@ -26,16 +26,16 @@ void gdsp_ifx_init()
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g_dsp.ifx_regs[i] = 0;
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g_dsp.ifx_regs[i] = 0;
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}
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}
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g_dsp.mbox[0].store(0);
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g_dsp.mbox[MAILBOX_CPU].store(0);
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g_dsp.mbox[1].store(0);
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g_dsp.mbox[MAILBOX_DSP].store(0);
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}
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}
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u32 gdsp_mbox_peek(u8 mbx)
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u32 gdsp_mbox_peek(Mailbox mbx)
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{
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{
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return g_dsp.mbox[mbx].load();
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return g_dsp.mbox[mbx].load();
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}
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}
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void gdsp_mbox_write_h(u8 mbx, u16 val)
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void gdsp_mbox_write_h(Mailbox mbx, u16 val)
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{
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{
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const u32 old_value = g_dsp.mbox[mbx].load(std::memory_order_acquire);
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const u32 old_value = g_dsp.mbox[mbx].load(std::memory_order_acquire);
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const u32 new_value = (old_value & 0xffff) | (val << 16);
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const u32 new_value = (old_value & 0xffff) | (val << 16);
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@ -43,7 +43,7 @@ void gdsp_mbox_write_h(u8 mbx, u16 val)
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g_dsp.mbox[mbx].store(new_value & ~0x80000000, std::memory_order_release);
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g_dsp.mbox[mbx].store(new_value & ~0x80000000, std::memory_order_release);
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}
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}
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void gdsp_mbox_write_l(u8 mbx, u16 val)
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void gdsp_mbox_write_l(Mailbox mbx, u16 val)
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{
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{
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const u32 old_value = g_dsp.mbox[mbx].load(std::memory_order_acquire);
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const u32 old_value = g_dsp.mbox[mbx].load(std::memory_order_acquire);
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const u32 new_value = (old_value & ~0xffff) | val;
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const u32 new_value = (old_value & ~0xffff) | val;
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@ -51,18 +51,16 @@ void gdsp_mbox_write_l(u8 mbx, u16 val)
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g_dsp.mbox[mbx].store(new_value | 0x80000000, std::memory_order_release);
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g_dsp.mbox[mbx].store(new_value | 0x80000000, std::memory_order_release);
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#if defined(_DEBUG) || defined(DEBUGFAST)
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#if defined(_DEBUG) || defined(DEBUGFAST)
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if (mbx == GDSP_MBOX_DSP)
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if (mbx == MAILBOX_DSP)
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{
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INFO_LOG(DSP_MAIL, "DSP(WM) B:%i M:0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(MAILBOX_DSP), g_dsp.pc);
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INFO_LOG(DSP_MAIL, "DSP(WM) B:%i M:0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_DSP), g_dsp.pc);
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else
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} else {
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INFO_LOG(DSP_MAIL, "CPU(WM) B:%i M:0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(MAILBOX_CPU), g_dsp.pc);
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INFO_LOG(DSP_MAIL, "CPU(WM) B:%i M:0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_CPU), g_dsp.pc);
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}
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#endif
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#endif
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}
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}
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u16 gdsp_mbox_read_h(u8 mbx)
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u16 gdsp_mbox_read_h(Mailbox mbx)
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{
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{
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if (init_hax && mbx)
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if (init_hax && mbx == MAILBOX_DSP)
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{
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{
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return 0x8054;
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return 0x8054;
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}
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}
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@ -70,12 +68,12 @@ u16 gdsp_mbox_read_h(u8 mbx)
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return (u16)(g_dsp.mbox[mbx].load() >> 16); // TODO: mask away the top bit?
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return (u16)(g_dsp.mbox[mbx].load() >> 16); // TODO: mask away the top bit?
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}
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}
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u16 gdsp_mbox_read_l(u8 mbx)
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u16 gdsp_mbox_read_l(Mailbox mbx)
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{
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{
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const u32 value = g_dsp.mbox[mbx].load(std::memory_order_acquire);
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const u32 value = g_dsp.mbox[mbx].load(std::memory_order_acquire);
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g_dsp.mbox[mbx].store(value & ~0x80000000, std::memory_order_release);
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g_dsp.mbox[mbx].store(value & ~0x80000000, std::memory_order_release);
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if (init_hax && mbx)
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if (init_hax && mbx == MAILBOX_DSP)
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{
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{
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init_hax = false;
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init_hax = false;
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DSPCore_Reset();
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DSPCore_Reset();
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@ -83,12 +81,10 @@ u16 gdsp_mbox_read_l(u8 mbx)
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}
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}
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#if defined(_DEBUG) || defined(DEBUGFAST)
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#if defined(_DEBUG) || defined(DEBUGFAST)
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if (mbx == GDSP_MBOX_DSP)
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if (mbx == MAILBOX_DSP)
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{
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INFO_LOG(DSP_MAIL, "DSP(RM) B:%i M:0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(MAILBOX_DSP), g_dsp.pc);
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INFO_LOG(DSP_MAIL, "DSP(RM) B:%i M:0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_DSP), g_dsp.pc);
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else
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} else {
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INFO_LOG(DSP_MAIL, "CPU(RM) B:%i M:0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(MAILBOX_CPU), g_dsp.pc);
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INFO_LOG(DSP_MAIL, "CPU(RM) B:%i M:0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_CPU), g_dsp.pc);
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}
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#endif
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#endif
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return (u16)value;
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return (u16)value;
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@ -108,18 +104,18 @@ void gdsp_ifx_write(u32 addr, u32 val)
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break;
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break;
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case DSP_DMBH:
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case DSP_DMBH:
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gdsp_mbox_write_h(GDSP_MBOX_DSP, val);
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gdsp_mbox_write_h(MAILBOX_DSP, val);
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break;
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break;
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case DSP_DMBL:
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case DSP_DMBL:
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gdsp_mbox_write_l(GDSP_MBOX_DSP, val);
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gdsp_mbox_write_l(MAILBOX_DSP, val);
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break;
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break;
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case DSP_CMBH:
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case DSP_CMBH:
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return gdsp_mbox_write_h(GDSP_MBOX_CPU, val);
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return gdsp_mbox_write_h(MAILBOX_CPU, val);
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case DSP_CMBL:
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case DSP_CMBL:
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return gdsp_mbox_write_l(GDSP_MBOX_CPU, val);
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return gdsp_mbox_write_l(MAILBOX_CPU, val);
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case DSP_DSBL:
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case DSP_DSBL:
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g_dsp.ifx_regs[DSP_DSBL] = val;
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g_dsp.ifx_regs[DSP_DSBL] = val;
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@ -178,16 +174,16 @@ static u16 _gdsp_ifx_read(u16 addr)
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switch (addr & 0xff)
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switch (addr & 0xff)
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{
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{
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case DSP_DMBH:
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case DSP_DMBH:
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return gdsp_mbox_read_h(GDSP_MBOX_DSP);
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return gdsp_mbox_read_h(MAILBOX_DSP);
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case DSP_DMBL:
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case DSP_DMBL:
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return gdsp_mbox_read_l(GDSP_MBOX_DSP);
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return gdsp_mbox_read_l(MAILBOX_DSP);
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case DSP_CMBH:
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case DSP_CMBH:
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return gdsp_mbox_read_h(GDSP_MBOX_CPU);
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return gdsp_mbox_read_h(MAILBOX_CPU);
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case DSP_CMBL:
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case DSP_CMBL:
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return gdsp_mbox_read_l(GDSP_MBOX_CPU);
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return gdsp_mbox_read_l(MAILBOX_CPU);
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case DSP_DSCR:
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case DSP_DSCR:
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return g_dsp.ifx_regs[addr & 0xFF];
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return g_dsp.ifx_regs[addr & 0xFF];
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@ -7,16 +7,18 @@
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#include "Common/CommonTypes.h"
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#include "Common/CommonTypes.h"
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#define GDSP_MBOX_CPU 0
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enum Mailbox
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#define GDSP_MBOX_DSP 1
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{
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MAILBOX_CPU,
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MAILBOX_DSP
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};
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u32 gdsp_mbox_peek(u8 mbx);
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u32 gdsp_mbox_peek(Mailbox mbx);
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void gdsp_mbox_write_h(u8 mbx, u16 val);
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void gdsp_mbox_write_h(Mailbox mbx, u16 val);
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void gdsp_mbox_write_l(u8 mbx, u16 val);
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void gdsp_mbox_write_l(Mailbox mbx, u16 val);
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u16 gdsp_mbox_read_h(u8 mbx);
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u16 gdsp_mbox_read_h(Mailbox mbx);
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u16 gdsp_mbox_read_l(u8 mbx);
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u16 gdsp_mbox_read_l(Mailbox mbx);
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void gdsp_ifx_init();
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void gdsp_ifx_init();
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void gdsp_ifx_write(u32 addr, u32 val);
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void gdsp_ifx_write(u32 addr, u32 val);
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u16 gdsp_ifx_read(u16 addr);
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u16 gdsp_ifx_read(u16 addr);
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@ -249,19 +249,19 @@ u16 DSPLLE::DSP_ReadControlRegister()
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u16 DSPLLE::DSP_ReadMailBoxHigh(bool _CPUMailbox)
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u16 DSPLLE::DSP_ReadMailBoxHigh(bool _CPUMailbox)
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{
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{
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return gdsp_mbox_read_h(_CPUMailbox ? GDSP_MBOX_CPU : GDSP_MBOX_DSP);
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return gdsp_mbox_read_h(_CPUMailbox ? MAILBOX_CPU : MAILBOX_DSP);
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}
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}
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u16 DSPLLE::DSP_ReadMailBoxLow(bool _CPUMailbox)
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u16 DSPLLE::DSP_ReadMailBoxLow(bool _CPUMailbox)
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{
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{
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return gdsp_mbox_read_l(_CPUMailbox ? GDSP_MBOX_CPU : GDSP_MBOX_DSP);
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return gdsp_mbox_read_l(_CPUMailbox ? MAILBOX_CPU : MAILBOX_DSP);
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}
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}
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void DSPLLE::DSP_WriteMailBoxHigh(bool _CPUMailbox, u16 _uHighMail)
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void DSPLLE::DSP_WriteMailBoxHigh(bool _CPUMailbox, u16 _uHighMail)
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{
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{
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if (_CPUMailbox)
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if (_CPUMailbox)
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{
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{
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if (gdsp_mbox_peek(GDSP_MBOX_CPU) & 0x80000000)
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if (gdsp_mbox_peek(MAILBOX_CPU) & 0x80000000)
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{
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{
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ERROR_LOG(DSPLLE, "Mailbox isnt empty ... strange");
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ERROR_LOG(DSPLLE, "Mailbox isnt empty ... strange");
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}
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}
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@ -273,7 +273,7 @@ void DSPLLE::DSP_WriteMailBoxHigh(bool _CPUMailbox, u16 _uHighMail)
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}
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}
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#endif
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#endif
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gdsp_mbox_write_h(GDSP_MBOX_CPU, _uHighMail);
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gdsp_mbox_write_h(MAILBOX_CPU, _uHighMail);
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}
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}
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else
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else
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{
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{
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@ -285,7 +285,7 @@ void DSPLLE::DSP_WriteMailBoxLow(bool _CPUMailbox, u16 _uLowMail)
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{
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{
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if (_CPUMailbox)
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if (_CPUMailbox)
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{
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{
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gdsp_mbox_write_l(GDSP_MBOX_CPU, _uLowMail);
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gdsp_mbox_write_l(MAILBOX_CPU, _uLowMail);
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}
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}
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else
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else
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{
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{
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