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MMU: Use MSR.IR for instruction reads.

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This commit is contained in:
Admiral H. Curtiss 2022-11-19 02:29:04 +01:00
parent c12725c916
commit a0da6788a3
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GPG Key ID: F051B4C4044F33FB
1 changed files with 4 additions and 3 deletions
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7
Source/Core/Core/PowerPC/MMU.cpp
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@ -172,7 +172,8 @@ T MMU::ReadFromHardware(u32 em_address)
bool wi = false; bool wi = false;
if (!never_translate && m_ppc_state.msr.DR) if (!never_translate &&
(IsOpcodeFlag(flag) ? m_ppc_state.msr.IR.Value() : m_ppc_state.msr.DR.Value()))
{ {
auto translated_addr = TranslateAddress<flag>(em_address); auto translated_addr = TranslateAddress<flag>(em_address);
if (!translated_addr.Success()) if (!translated_addr.Success())
@ -516,7 +517,7 @@ std::optional<ReadResult<u32>> MMU::HostTryReadInstruction(const Core::CPUThread
case RequestedAddressSpace::Effective: case RequestedAddressSpace::Effective:
{ {
const u32 value = mmu.ReadFromHardware<XCheckTLBFlag::OpcodeNoException, u32>(address); const u32 value = mmu.ReadFromHardware<XCheckTLBFlag::OpcodeNoException, u32>(address);
return ReadResult<u32>(!!mmu.m_ppc_state.msr.DR, value); return ReadResult<u32>(!!mmu.m_ppc_state.msr.IR, value);
} }
case RequestedAddressSpace::Physical: case RequestedAddressSpace::Physical:
{ {
@ -525,7 +526,7 @@ std::optional<ReadResult<u32>> MMU::HostTryReadInstruction(const Core::CPUThread
} }
case RequestedAddressSpace::Virtual: case RequestedAddressSpace::Virtual:
{ {
if (!mmu.m_ppc_state.msr.DR) if (!mmu.m_ppc_state.msr.IR)
return std::nullopt; return std::nullopt;
const u32 value = mmu.ReadFromHardware<XCheckTLBFlag::OpcodeNoException, u32>(address); const u32 value = mmu.ReadFromHardware<XCheckTLBFlag::OpcodeNoException, u32>(address);
return ReadResult<u32>(true, value); return ReadResult<u32>(true, value);