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Merge pull request #1492 from FioraAeterna/fixregpreload
JIT: fix register preloading
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commit
a66b34cfc6
@ -747,12 +747,12 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
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if (ops[i].gprInReg[reg] && !gpr.R(reg).IsImm())
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gpr.BindToRegister(reg, true, false);
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}
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for (int reg : ops[i].regsOut)
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for (int reg : ops[i].fregsIn)
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{
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if (fpr.NumFreeRegisters() < 2)
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break;
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if (ops[i].fprInXmm[reg])
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gpr.BindToRegister(reg, true, false);
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fpr.BindToRegister(reg, true, false);
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}
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Jit64Tables::CompileInstruction(ops[i]);
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