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DSP: Comment the DSPSpy ucode a bit.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2997 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -1,4 +1,6 @@
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; This is the trojan program we send to the DSP from DSPSpy to figure it out.
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; A lot of constant definitions.
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DSCR: equ 0xffc9 ; DSP DMA Control Reg
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DSCR: equ 0xffc9 ; DSP DMA Control Reg
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DSBL: equ 0xffcb ; DSP DMA Block Length
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DSBL: equ 0xffcb ; DSP DMA Block Length
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DSPA: equ 0xffcd ; DSP DMA DMEM Address
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DSPA: equ 0xffcd ; DSP DMA DMEM Address
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@ -65,6 +67,7 @@ REGS_BASE: equ 0x0f80
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MEM_HI: equ 0x0f7E
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MEM_HI: equ 0x0f7E
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MEM_LO: equ 0x0f7F
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MEM_LO: equ 0x0f7F
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; CODE STARTS HERE.
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; Interrupt vectors 8 vectors, 2 opcodes each
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; Interrupt vectors 8 vectors, 2 opcodes each
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@ -78,21 +81,22 @@ MEM_LO: equ 0x0f7F
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jmp irq7
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jmp irq7
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; Main code at 0x10
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; Main code at 0x10
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CW 0x1302
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sbset #0x02
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CW 0x1303
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sbset #0x03
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CW 0x1204
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sbclr #0x04
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CW 0x1305
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sbset #0x05
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CW 0x1306
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sbset #0x06
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s40
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s40
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lri $r12, #0x00ff
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lri $CR, #0x00ff
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; Why do we have a main label here?
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main:
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main:
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cw 0x8900
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clr $ACC1
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cw 0x8100
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clr $ACC0
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; get address of memory dump and copy it
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; get address of memory dump and copy it to DRAM
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call wait_for_dsp_mbox
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call wait_for_dsp_mbox
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si @DMBH, #0x8888
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si @DMBH, #0x8888
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@ -114,7 +118,7 @@ main:
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call do_dma
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call do_dma
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; get address of registers and DMA them to memory
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; get address of registers and DMA them to ram
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call wait_for_dsp_mbox
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call wait_for_dsp_mbox
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si @DMBH, #0x8888
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si @DMBH, #0x8888
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@ -135,7 +139,7 @@ main:
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lr $r1e, @MEM_LO
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lr $r1e, @MEM_LO
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call do_dma
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call do_dma
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; Read in all the registers from RAM
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lri $r00, #REGS_BASE+1
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lri $r00, #REGS_BASE+1
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lrri $r01, @$r00
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lrri $r01, @$r00
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@ -171,27 +175,29 @@ main:
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lrri $r1f, @$r00
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lrri $r1f, @$r00
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lr $r00, @REGS_BASE
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lr $r00, @REGS_BASE
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; Right here we are at a specific predetermined state.
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; Ideal environment to try instructions.
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; We can call send_back at any time to send data back to the PowerPC.
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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cw 0x8600
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call send_back
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; We're done - currently we only test one opcode, in this case 0x8600.
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cw 0x8600
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; It's possible to test many more in one go - just call send_back after each one.
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call send_back
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jmp ende
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JMP ende
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; Below here is tons of random leftover test code from whoever last experimented with this.
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; call dump_memory
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; call dump_memory
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; call send_back
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; call send_back
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; 0x041e
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;
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cw 0x00de
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cw 0x00de
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cw 0x03f1
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cw 0x03f1
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@ -405,7 +411,7 @@ g_0c65:
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call send_back
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call send_back
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; This is where we jump when we're done testing, see above.
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ende:
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ende:
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nop
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nop
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@ -416,36 +422,42 @@ ende:
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nop
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nop
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nop
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nop
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; We just fall into a loop, playing dead until someone resets the DSP.
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dead_loop:
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dead_loop:
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jmp dead_loop
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jmp dead_loop
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; Utility function to do DMA.
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; r1c:r1e - external address.
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; r18 - address in DSP
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do_dma:
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do_dma:
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sr @DSMAH, $r1c
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sr @DSMAH, $r1c
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sr @DSMAL, $r1e
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sr @DSMAL, $r1e
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sr @DSPA, $r18
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sr @DSPA, $r18
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sr @DSCR, $r19
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sr @DSCR, $r19
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sr @DSBL, $r1a
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sr @DSBL, $r1a ; This kicks off the DMA.
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; Waits for said DMA to complete by watching a bit in DSCR.
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wait_dma:
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wait_dma:
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LRS $ACL1, @DSCR
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LRS $ACL1, @DSCR
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andcf $acl1, #0x0004
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andcf $acl1, #0x0004
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JLZ wait_dma
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JLZ wait_dma
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RET
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RET
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; This waits for a mail to arrive in the DSP in-mailbox.
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wait_for_dsp_mbox:
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wait_for_dsp_mbox:
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lrs $ACL1, @DMBH
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lrs $ACL1, @DMBH
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andcf $acl1, #0x8000
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andcf $acl1, #0x8000
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jlz wait_for_dsp_mbox
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jlz wait_for_dsp_mbox
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ret
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ret
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; This waits for the CPU to grab a mail that we just sent from the DSP.
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wait_for_cpu_mbox:
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wait_for_cpu_mbox:
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lrs $ACL1, @cmbh
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lrs $ACL1, @cmbh
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andcf $acl1, #0x8000
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andcf $acl1, #0x8000
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jlnz wait_for_cpu_mbox
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jlnz wait_for_cpu_mbox
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ret
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ret
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; IRQ handlers. Not entirely sure what good they do currently.
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irq0:
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irq0:
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lri $acl0, #0x0000
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lri $acl0, #0x0000
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jmp irq
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jmp irq
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@ -455,7 +467,6 @@ irq1:
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irq2:
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irq2:
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lri $acl0, #0x0002
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lri $acl0, #0x0002
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jmp irq
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jmp irq
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irq3:
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irq3:
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lri $acl0, #0x0003
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lri $acl0, #0x0003
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jmp irq
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jmp irq
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@ -463,14 +474,14 @@ irq4:
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lri $acl0, #0x0004
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lri $acl0, #0x0004
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jmp irq
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jmp irq
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irq5:
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irq5:
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; jmp finale
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; No idea what this code is doing.
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s40
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s40
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mrr $r0d, $r1c
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mrr $r0d, $r1c
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mrr $r0d, $r1e
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mrr $r0d, $r1e
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clr $acc0
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clr $acc0
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mrr $r1e, $r0d
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mrr $r1e, $r0d
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mrr $r1c, $r0d
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mrr $r1c, $r0d
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nop
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nop ; Or why there's a nop sled here.
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nop
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nop
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nop
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nop
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nop
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nop
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@ -486,7 +497,7 @@ irq6:
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irq7:
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irq7:
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lri $acl0, #0x0007
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lri $acl0, #0x0007
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jmp irq
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jmp irq
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irq:
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irq:
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lrs $ACL1, @DMBH
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lrs $ACL1, @DMBH
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andcf $acl1, #0x8000
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andcf $acl1, #0x8000
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@ -497,11 +508,9 @@ irq:
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si @DIRQ, #0x0001
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si @DIRQ, #0x0001
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halt
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halt
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; DMA:s the current state of the registers back to the PowerPC. To do this,
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; it must write the contents of all regs to DRAM.
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send_back:
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send_back:
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; store registers to reg table
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; store registers to reg table
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sr @REGS_BASE, $r00
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sr @REGS_BASE, $r00
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lri $r00, #(REGS_BASE + 1)
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lri $r00, #(REGS_BASE + 1)
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@ -536,8 +545,8 @@ send_back:
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srri @$r00, $r1d
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srri @$r00, $r1d
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srri @$r00, $r1e
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srri @$r00, $r1e
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srri @$r00, $r1f
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srri @$r00, $r1f
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; Regs are stored. Prepare DMA.
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lri $r18, #0x0000
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lri $r18, #0x0000
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lri $r19, #1 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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lri $r19, #1 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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lri $r1a, #0x200
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lri $r1a, #0x200
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@ -545,7 +554,8 @@ send_back:
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lr $r1e, @MEM_LO
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lr $r1e, @MEM_LO
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lri $r01, #8+8
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lri $r01, #8+8
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; Now, why are we looping here?
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bloop $r01, dma_copy
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bloop $r01, dma_copy
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call do_dma
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call do_dma
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addi $r1e, #0x200
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addi $r1e, #0x200
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@ -553,21 +563,22 @@ send_back:
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addi $r1f, #0x100
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addi $r1f, #0x100
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mrr $r18, $r1f
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mrr $r18, $r1f
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nop
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nop
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dma_copy:
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dma_copy:
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nop
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nop
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; Wait for the CPU to send us a mail.
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call wait_for_dsp_mbox
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call wait_for_dsp_mbox
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si @DMBH, #0x8888
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si @DMBH, #0x8888
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si @DMBL, #0xfeeb
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si @DMBL, #0xfeeb
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si @DIRQ, #0x0001
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si @DIRQ, #0x0001
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; wait for answer before we execute the next op
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; wait for the CPU to recieve our response before we execute the next op
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call wait_for_cpu_mbox
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call wait_for_cpu_mbox
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lrs $ACL0, @CMBL
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lrs $ACL0, @CMBL
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andi $acl1, #0x7fff
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andi $acl1, #0x7fff
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; Restore all regs again so we're ready to execute another op.
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lri $r00, #REGS_BASE+1
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lri $r00, #REGS_BASE+1
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lrri $r01, @$r00
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lrri $r01, @$r00
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lrri $r02, @$r00
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lrri $r02, @$r00
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@ -602,19 +613,18 @@ dma_copy:
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lrri $r1f, @$r00
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lrri $r1f, @$r00
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lr $r00, @REGS_BASE
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lr $r00, @REGS_BASE
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ret
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ret ; from send_back
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; I wish I knew what this 16 means.
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send_back_16:
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send_back_16:
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set40
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cw 0x8e00
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call send_back
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call send_back
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cw 0x8f00
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set16
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ret
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ret
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dump_memory:
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; This one's odd. Doesn't look like it should work since it uses acl0 but
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; increments acm0... (acc0)
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dump_memory:
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lri $r02, #0x0000
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lri $r02, #0x0000
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lri $acl0, #0x1000
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lri $acl0, #0x1000
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@ -622,18 +632,16 @@ dump_memory:
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bloop $r01, _fill_loop2
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bloop $r01, _fill_loop2
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mrr $r03, $acl0
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mrr $r03, $acl0
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cw 0x80f0
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nx'ld : $AX0.H, $AX1.H, @$AR0
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mrr $r1f, $r00
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mrr $r1f, $r00
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mrr $r00, $r02
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mrr $r00, $r02
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srri @$r00, $r1b
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srri @$r00, $r1b
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mrr $r02, $r00
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mrr $r02, $r00
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mrr $r00, $r1f
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mrr $r00, $r1f
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addis $acc0, #0x1
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addis $acc0, #0x1
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_fill_loop2:
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_fill_loop2:
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nop
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nop
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ret ; from dump_memory
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ret
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