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Arm64Emitter: Don't optimize ADD to MOV for SP

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Unlike ADD (immediate), MOV (register) treats SP as ZR. Therefore the
ADDI2R optimization that was added in 67791d227c can't optimize ADD to
MOV when exactly one of the registers is SP.

There currently isn't any code in Dolphin that calls ADDI2R with
parameters that would trigger this case.
This commit is contained in:
JosJuice 2024-02-06 21:58:07 +01:00
parent 9240f579ea
commit b5c5371848
1 changed files with 8 additions and 2 deletions
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10
Source/Core/Common/Arm64Emitter.cpp
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@ -4222,9 +4222,15 @@ void ARM64XEmitter::ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool nega
// Special path for zeroes // Special path for zeroes
if (imm == 0 && !flags) if (imm == 0 && !flags)
{ {
if (Rd != Rn) if (Rd == Rn)
{
return;
}
else if (DecodeReg(Rd) != DecodeReg(ARM64Reg::SP) && DecodeReg(Rn) != DecodeReg(ARM64Reg::SP))
{
MOV(Rd, Rn); MOV(Rd, Rn);
return; return;
}
} }
// Regular fast paths, aarch64 immediate instructions // Regular fast paths, aarch64 immediate instructions