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Workaround for a missing feature in the FPU parts of the JIT.

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git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@246 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
hrydgard 2008-08-20 18:27:20 +00:00
parent c6580d1712
commit b5ff3fd80e
5 changed files with 45 additions and 1 deletions
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6
Source/Core/Core/Src/PowerPC/Jit64/JitAsm.cpp
View File

@ -48,6 +48,7 @@ const u8 *dispatcher;
const u8 *dispatcherNoCheck;
const u8 *dispatcherPcInEAX;
const u8 *computeRc;
const u8 *computeRcFp;
const u8 *fifoDirectWrite8;
const u8 *fifoDirectWrite16;
@ -336,6 +337,11 @@ void GenerateCommon()
GenFifoWrite(32);
fifoDirectWriteFloat = AlignCode4();
GenFifoFloatWrite();
computeRcFp = AlignCode16();
//CMPSD(R(XMM0), M(&zero),
// TODO
// Fast write routines - special case the most common hardware write
// TODO: use this.
// Even in x86, the param values will be in the right registers.

1
Source/Core/Core/Src/PowerPC/Jit64/JitAsm.h
View File

@ -30,6 +30,7 @@ namespace Jit64
extern const u8 *fpException;
extern const u8 *computeRc;
extern const u8 *computeRcFp;
extern const u8 *testExceptions;
extern const u8 *dispatchPcInEAX;
extern const u8 *doTiming;

6
Source/Core/Core/Src/PowerPC/Jit64/JitRegCache.cpp
View File

@ -349,8 +349,12 @@ namespace Jit64
xregs[xr].free = false;
xregs[xr].dirty = makeDirty;
OpArg newloc = ::Gen::R(xr);
if (doLoad)
if (doLoad) {
if (!regs[i].location.IsImm() && (regs[i].location.offset & 0xF)) {
PanicAlert("WARNING - misaligned fp register location %i", i);
}
MOVAPD(xr, regs[i].location);
}
regs[i].location = newloc;
regs[i].away = true;
}

9
Source/Core/Core/Src/PowerPC/Jit64/Jit_FloatingPoint.cpp
View File

@ -79,6 +79,9 @@ namespace Jit64
void fp_arith_s(UGeckoInstruction inst)
{
INSTRUCTION_START;
if (inst.Rc) {
Default(inst); return;
}
bool dupe = inst.OPCD == 59;
switch (inst.SUBOP5)
{
@ -100,6 +103,9 @@ namespace Jit64
void fmaddXX(UGeckoInstruction inst)
{
INSTRUCTION_START;
if (inst.Rc) {
Default(inst); return;
}
int a = inst.FA;
int b = inst.FB;
int c = inst.FC;
@ -139,6 +145,9 @@ namespace Jit64
void fmrx(UGeckoInstruction inst)
{
INSTRUCTION_START;
if (inst.Rc) {
Default(inst); return;
}
int d = inst.FD;
int b = inst.FB;
fpr.LoadToX64(d, true); // we don't want to destroy the high bit

24
Source/Core/Core/Src/PowerPC/Jit64/Jit_Paired.cpp
View File

@ -53,6 +53,9 @@ namespace Jit64
void ps_mr(UGeckoInstruction inst)
{
INSTRUCTION_START;
if (inst.Rc) {
Default(inst); return;
}
int d = inst.FD;
int b = inst.FB;
if (d == b)
@ -67,6 +70,9 @@ namespace Jit64
Default(inst);
return;
if (inst.Rc) {
Default(inst); return;
}
// GRR can't get this to work 100%. Getting artifacts in D.O.N. intro.
int d = inst.FD;
int a = inst.FA;
@ -92,6 +98,9 @@ namespace Jit64
void ps_sign(UGeckoInstruction inst)
{
INSTRUCTION_START;
if (inst.Rc) {
Default(inst); return;
}
int d = inst.FD;
int b = inst.FB;
@ -125,6 +134,9 @@ namespace Jit64
void ps_rsqrte(UGeckoInstruction inst)
{
INSTRUCTION_START;
if (inst.Rc) {
Default(inst); return;
}
int d = inst.FD;
int b = inst.FB;
fpr.Lock(d, b);
@ -193,6 +205,9 @@ namespace Jit64
void ps_arith(UGeckoInstruction inst)
{
INSTRUCTION_START;
if (inst.Rc) {
Default(inst); return;
}
switch (inst.SUBOP5)
{
case 18: tri_op(inst.FD, inst.FA, inst.FB, false, &DIVPD); break; //div
@ -214,6 +229,9 @@ namespace Jit64
void ps_mergeXX(UGeckoInstruction inst)
{
INSTRUCTION_START;
if (inst.Rc) {
Default(inst); return;
}
int d = inst.FD;
int a = inst.FA;
int b = inst.FB;
@ -252,6 +270,9 @@ namespace Jit64
void ps_maddXX(UGeckoInstruction inst)
{
INSTRUCTION_START;
if (inst.Rc) {
Default(inst); return;
}
int a = inst.FA;
int b = inst.FB;
int c = inst.FC;
@ -295,6 +316,9 @@ namespace Jit64
INSTRUCTION_START;
Default(inst);
return;
if (inst.Rc) {
Default(inst); return;
}
switch (inst.SUBOP5)
{