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Add conditional register cache flushing to JIT64's bcctrx conditional route.

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This commit is contained in:
Ryan Houdek 2014-06-10 02:44:16 -05:00
parent 5e1a465d50
commit b99edd6202
1 changed files with 6 additions and 3 deletions
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9
Source/Core/Core/PowerPC/Jit64/Jit_Branch.cpp
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@ -155,9 +155,6 @@ void Jit64::bcctrx(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITBranchOff) JITDISABLE(bJITBranchOff)
gpr.Flush();
fpr.Flush();
// bcctrx doesn't decrement and/or test CTR // bcctrx doesn't decrement and/or test CTR
_dbg_assert_msg_(POWERPC, inst.BO_2 & BO_DONT_DECREMENT_FLAG, "bcctrx with decrement and test CTR option is invalid!"); _dbg_assert_msg_(POWERPC, inst.BO_2 & BO_DONT_DECREMENT_FLAG, "bcctrx with decrement and test CTR option is invalid!");
@ -166,6 +163,9 @@ void Jit64::bcctrx(UGeckoInstruction inst)
// BO_2 == 1z1zz -> b always // BO_2 == 1z1zz -> b always
//NPC = CTR & 0xfffffffc; //NPC = CTR & 0xfffffffc;
gpr.Flush();
fpr.Flush();
MOV(32, R(EAX), M(&CTR)); MOV(32, R(EAX), M(&CTR));
if (inst.LK_3) if (inst.LK_3)
MOV(32, M(&LR), Imm32(js.compilerPC + 4)); // LR = PC + 4; MOV(32, M(&LR), Imm32(js.compilerPC + 4)); // LR = PC + 4;
@ -192,6 +192,9 @@ void Jit64::bcctrx(UGeckoInstruction inst)
//MOV(32, M(&PC), R(EAX)); => Already done in WriteExitDestInEAX() //MOV(32, M(&PC), R(EAX)); => Already done in WriteExitDestInEAX()
if (inst.LK_3) if (inst.LK_3)
MOV(32, M(&LR), Imm32(js.compilerPC + 4)); // LR = PC + 4; MOV(32, M(&LR), Imm32(js.compilerPC + 4)); // LR = PC + 4;
gpr.Flush(FLUSH_MAINTAIN_STATE);
fpr.Flush(FLUSH_MAINTAIN_STATE);
WriteExitDestInEAX(); WriteExitDestInEAX();
// Would really like to continue the block here, but it ends. TODO. // Would really like to continue the block here, but it ends. TODO.
SetJumpTarget(b); SetJumpTarget(b);