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Merge pull request #1940 from Sonicadvance1/AArch64_implement_xer
[AArch64] Implement mfspr/mtspr XER routines.
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commit
bb1ca26c57
@ -206,6 +206,18 @@ void JitArm64::mfspr(UGeckoInstruction inst)
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switch (iIndex)
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{
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case SPR_XER:
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{
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gpr.BindToRegister(inst.RD, false);
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ARM64Reg RD = gpr.R(inst.RD);
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ARM64Reg WA = gpr.GetReg();
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LDRH(INDEX_UNSIGNED, RD, X29, PPCSTATE_OFF(xer_stringctrl));
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LDRB(INDEX_UNSIGNED, WA, X29, PPCSTATE_OFF(xer_ca));
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ORR(RD, RD, WA, ArithOption(WA, ST_LSL, XER_CA_SHIFT));
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LDRB(INDEX_UNSIGNED, WA, X29, PPCSTATE_OFF(xer_so_ov));
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ORR(RD, RD, WA, ArithOption(WA, ST_LSL, XER_OV_SHIFT));
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gpr.Unlock(WA);
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}
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break;
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case SPR_WPAR:
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case SPR_DEC:
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case SPR_TL:
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@ -261,18 +273,15 @@ void JitArm64::mtspr(UGeckoInstruction inst)
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break;
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case SPR_XER:
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{
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FALLBACK_IF(true);
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ARM64Reg RD = gpr.R(inst.RD);
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ARM64Reg WA = gpr.GetReg();
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ARM64Reg mask = gpr.GetReg();
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MOVI2R(mask, 0xFF7F);
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AND(WA, RD, mask, ArithOption(mask, ST_LSL, 0));
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AND(WA, RD, 24, 30);
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STRH(INDEX_UNSIGNED, WA, X29, PPCSTATE_OFF(xer_stringctrl));
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UBFM(WA, RD, XER_CA_SHIFT, XER_CA_SHIFT);
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UBFM(WA, RD, XER_CA_SHIFT, XER_CA_SHIFT + 1);
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STRB(INDEX_UNSIGNED, WA, X29, PPCSTATE_OFF(xer_ca));
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UBFM(WA, RD, XER_OV_SHIFT, 31); // Same as WA = RD >> XER_OV_SHIFT
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STRB(INDEX_UNSIGNED, WA, X29, PPCSTATE_OFF(xer_so_ov));
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gpr.Unlock(WA, mask);
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gpr.Unlock(WA);
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}
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break;
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default:
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