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* CPUID changes:
- Added full ability to recognize true Intel HTT CPU capability (support to discriminate Intel Core 2 Duo...) - Attempt to fix a register trashing (issue 4022 generally, linux and mac systems) git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@7097 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -35,29 +35,20 @@
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static inline void do_cpuid(unsigned int *eax, unsigned int *ebx,
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static inline void do_cpuid(unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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unsigned int *ecx, unsigned int *edx)
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{
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{
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#ifdef _LP64
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// Note: EBX is reserved on Mac OS X and in PIC on Linux, so it has to be
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__asm__("cpuid"
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// restored at the end of the asm block.
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: "=a" (*eax),
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__asm__(
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"=b" (*ebx),
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"pushl %%ebx;"
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"=c" (*ecx),
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"cpuid;"
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"=d" (*edx)
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"movl %%ebx,%1;"
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: "a" (*eax)
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"popl %%ebx;"
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);
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: "=a" (*eax),
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#else
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"=r" (*ebx),
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// Note: EBX is reserved on Mac OS X and in PIC on Linux, so it has to be
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"=c" (*ecx),
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// restored at the end of the asm block.
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"=d" (*edx)
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__asm__(
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: "a" (*eax)
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"pushl %%ebx;"
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: "eax", "ebx", "ecx", "edx" // clobbered registers
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"cpuid;"
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);
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"movl %%ebx,%1;"
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"popl %%ebx;"
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: "=a" (*eax),
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"=r" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "a" (*eax)
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);
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#endif
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}
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}
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static void __cpuid(int info[4], int x)
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static void __cpuid(int info[4], int x)
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@ -140,8 +131,7 @@ void CPUInfo::Detect()
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__cpuid(cpu_id, 0x00000001);
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__cpuid(cpu_id, 0x00000001);
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logical_cpu_count = (cpu_id[1] >> 16) & 0xFF;
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logical_cpu_count = (cpu_id[1] >> 16) & 0xFF;
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ht = (cpu_id[3] >> 28) & 1;
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ht = (cpu_id[3] >> 28) & 1;
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// True HTT is valid for intel processors only.
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HTT = (ht && vendor == VENDOR_INTEL);
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if ((cpu_id[3] >> 25) & 1) bSSE = true;
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if ((cpu_id[3] >> 25) & 1) bSSE = true;
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if ((cpu_id[3] >> 26) & 1) bSSE2 = true;
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if ((cpu_id[3] >> 26) & 1) bSSE2 = true;
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if ((cpu_id[2]) & 1) bSSE3 = true;
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if ((cpu_id[2]) & 1) bSSE3 = true;
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@ -177,18 +167,18 @@ void CPUInfo::Detect()
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int apic_id_core_id_size = (cpu_id[2] >> 12) & 0xF;
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int apic_id_core_id_size = (cpu_id[2] >> 12) & 0xF;
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if (apic_id_core_id_size == 0) {
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if (apic_id_core_id_size == 0) {
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if (ht) {
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if (ht) {
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if (vendor == VENDOR_OTHER) {
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num_cores = 1;
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}
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// New mechanism for modern Intel CPUs.
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// New mechanism for modern Intel CPUs.
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if (HTT) {
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if (vendor == VENDOR_INTEL) {
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__cpuid(cpu_id, 0x00000004);
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__cpuid(cpu_id, 0x00000004);
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int cores_x_package = ((cpu_id[0] >> 26) & 0x3F) + 1;
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int cores_x_package = ((cpu_id[0] >> 26) & 0x3F) + 1;
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HTT = (cores_x_package < logical_cpu_count);
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cores_x_package = ((logical_cpu_count % cores_x_package) == 0) ? cores_x_package : 1;
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cores_x_package = ((logical_cpu_count % cores_x_package) == 0) ? cores_x_package : 1;
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num_cores = (cores_x_package > 1) ? cores_x_package : num_cores;
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num_cores = (cores_x_package > 1) ? cores_x_package : num_cores;
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logical_cpu_count /= cores_x_package;
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logical_cpu_count /= cores_x_package;
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} else if (vendor == VENDOR_OTHER) { //trash block!!??
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num_cores = 1;
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}
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}
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} else {
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} else { //trash block!!??
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num_cores = 1;
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num_cores = 1;
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}
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}
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} else {
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} else {
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@ -207,7 +197,7 @@ std::string CPUInfo::Summarize()
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else
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else
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{
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{
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sum = StringFromFormat("%s, %i cores", cpu_string, num_cores);
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sum = StringFromFormat("%s, %i cores", cpu_string, num_cores);
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if (HTT) sum += StringFromFormat(" (%i logical thread(s) per physical core)", logical_cpu_count);
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if (HTT) sum += StringFromFormat(" (%i logical threads per physical core)", logical_cpu_count);
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}
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}
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if (bSSE) sum += ", SSE";
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if (bSSE) sum += ", SSE";
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if (bSSE2) sum += ", SSE2";
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if (bSSE2) sum += ", SSE2";
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@ -215,6 +205,7 @@ std::string CPUInfo::Summarize()
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if (bSSSE3) sum += ", SSSE3";
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if (bSSSE3) sum += ", SSSE3";
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if (bSSE4_1) sum += ", SSE4.1";
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if (bSSE4_1) sum += ", SSE4.1";
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if (bSSE4_2) sum += ", SSE4.2";
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if (bSSE4_2) sum += ", SSE4.2";
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if (HTT) sum += ", HTT";
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if (bAVX) sum += ", AVX";
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if (bAVX) sum += ", AVX";
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if (bAES) sum += ", AES";
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if (bAES) sum += ", AES";
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if (bLongMode) sum += ", 64-bit support";
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if (bLongMode) sum += ", 64-bit support";
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