From 84375a91d9673b70bed91d567cd0ee48030205f1 Mon Sep 17 00:00:00 2001 From: JosJuice Date: Wed, 19 Oct 2022 20:20:39 +0200 Subject: [PATCH] Arm64Emitter: Combine immh and immb for Emit(Scalar)ShiftImm This simplifies the callers of EmitShiftImm and EmitScalarShiftImm. --- Source/Core/Common/Arm64Emitter.cpp | 82 ++++++----------------------- Source/Core/Common/Arm64Emitter.h | 4 +- 2 files changed, 17 insertions(+), 69 deletions(-) diff --git a/Source/Core/Common/Arm64Emitter.cpp b/Source/Core/Common/Arm64Emitter.cpp index 013285329f..2d6531503b 100644 --- a/Source/Core/Common/Arm64Emitter.cpp +++ b/Source/Core/Common/Arm64Emitter.cpp @@ -2344,20 +2344,18 @@ void ARM64FloatEmitter::EmitScalarImm(bool M, bool S, u32 type, u32 imm5, ARM64R (1 << 12) | (imm5 << 5) | DecodeReg(Rd)); } -void ARM64FloatEmitter::EmitShiftImm(bool Q, bool U, u32 immh, u32 immb, u32 opcode, ARM64Reg Rd, - ARM64Reg Rn) +void ARM64FloatEmitter::EmitShiftImm(bool Q, bool U, u32 imm, u32 opcode, ARM64Reg Rd, ARM64Reg Rn) { - ASSERT_MSG(DYNA_REC, immh != 0, "Can't have zero immh"); + ASSERT_MSG(DYNA_REC, (imm & 0b1111000) != 0, "Can't have zero immh"); - Write32((Q << 30) | (U << 29) | (0xF << 24) | (immh << 19) | (immb << 16) | (opcode << 11) | - (1 << 10) | (DecodeReg(Rn) << 5) | DecodeReg(Rd)); + Write32((Q << 30) | (U << 29) | (0xF << 24) | (imm << 16) | (opcode << 11) | (1 << 10) | + (DecodeReg(Rn) << 5) | DecodeReg(Rd)); } -void ARM64FloatEmitter::EmitScalarShiftImm(bool U, u32 immh, u32 immb, u32 opcode, ARM64Reg Rd, - ARM64Reg Rn) +void ARM64FloatEmitter::EmitScalarShiftImm(bool U, u32 imm, u32 opcode, ARM64Reg Rd, ARM64Reg Rn) { - Write32((2 << 30) | (U << 29) | (0x3E << 23) | (immh << 19) | (immb << 16) | (opcode << 11) | - (1 << 10) | (DecodeReg(Rn) << 5) | DecodeReg(Rd)); + Write32((2 << 30) | (U << 29) | (0x3E << 23) | (imm << 16) | (opcode << 11) | (1 << 10) | + (DecodeReg(Rn) << 5) | DecodeReg(Rd)); } void ARM64FloatEmitter::EmitLoadStoreMultipleStructure(u32 size, bool L, u32 opcode, ARM64Reg Rt, @@ -3207,13 +3205,11 @@ void ARM64FloatEmitter::UCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn) } void ARM64FloatEmitter::SCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn, int scale) { - int imm = size * 2 - scale; - EmitShiftImm(IsQuad(Rd), 0, imm >> 3, imm & 7, 0x1C, Rd, Rn); + EmitShiftImm(IsQuad(Rd), 0, size * 2 - scale, 0x1C, Rd, Rn); } void ARM64FloatEmitter::UCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn, int scale) { - int imm = size * 2 - scale; - EmitShiftImm(IsQuad(Rd), 1, imm >> 3, imm & 7, 0x1C, Rd, Rn); + EmitShiftImm(IsQuad(Rd), 1, size * 2 - scale, 0x1C, Rd, Rn); } void ARM64FloatEmitter::SQXTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn) { @@ -3588,71 +3584,23 @@ void ARM64FloatEmitter::UXTL2(u8 src_size, ARM64Reg Rd, ARM64Reg Rn) void ARM64FloatEmitter::SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper) { - ASSERT_MSG(DYNA_REC, shift < src_size, "Shift amount must less than the element size! {} {}", + ASSERT_MSG(DYNA_REC, shift < src_size, "Shift amount must be less than the element size! {} {}", shift, src_size); - u32 immh = 0; - u32 immb = shift & 0xFFF; - - if (src_size == 8) - { - immh = 1; - } - else if (src_size == 16) - { - immh = 2 | ((shift >> 3) & 1); - } - else if (src_size == 32) - { - immh = 4 | ((shift >> 3) & 3); - ; - } - EmitShiftImm(upper, 0, immh, immb, 0b10100, Rd, Rn); + EmitShiftImm(upper, 0, src_size | shift, 0b10100, Rd, Rn); } void ARM64FloatEmitter::USHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper) { - ASSERT_MSG(DYNA_REC, shift < src_size, "Shift amount must less than the element size! {} {}", + ASSERT_MSG(DYNA_REC, shift < src_size, "Shift amount must be less than the element size! {} {}", shift, src_size); - u32 immh = 0; - u32 immb = shift & 0xFFF; - - if (src_size == 8) - { - immh = 1; - } - else if (src_size == 16) - { - immh = 2 | ((shift >> 3) & 1); - } - else if (src_size == 32) - { - immh = 4 | ((shift >> 3) & 3); - ; - } - EmitShiftImm(upper, 1, immh, immb, 0b10100, Rd, Rn); + EmitShiftImm(upper, 1, src_size | shift, 0b10100, Rd, Rn); } void ARM64FloatEmitter::SHRN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper) { - ASSERT_MSG(DYNA_REC, shift < dest_size, "Shift amount must less than the element size! {} {}", + ASSERT_MSG(DYNA_REC, shift < dest_size, "Shift amount must be less than the element size! {} {}", shift, dest_size); - u32 immh = 0; - u32 immb = shift & 0xFFF; - - if (dest_size == 8) - { - immh = 1; - } - else if (dest_size == 16) - { - immh = 2 | ((shift >> 3) & 1); - } - else if (dest_size == 32) - { - immh = 4 | ((shift >> 3) & 3); - ; - } - EmitShiftImm(upper, 1, immh, immb, 0b10000, Rd, Rn); + EmitShiftImm(upper, 1, dest_size | shift, 0b10000, Rd, Rn); } void ARM64FloatEmitter::SXTL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, bool upper) diff --git a/Source/Core/Common/Arm64Emitter.h b/Source/Core/Common/Arm64Emitter.h index e1f237c39f..a180b5282c 100644 --- a/Source/Core/Common/Arm64Emitter.h +++ b/Source/Core/Common/Arm64Emitter.h @@ -1282,8 +1282,8 @@ private: void EmitCondSelect(bool M, bool S, CCFlags cond, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm); void EmitPermute(u32 size, u32 op, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm); void EmitScalarImm(bool M, bool S, u32 type, u32 imm5, ARM64Reg Rd, u32 imm8); - void EmitShiftImm(bool Q, bool U, u32 immh, u32 immb, u32 opcode, ARM64Reg Rd, ARM64Reg Rn); - void EmitScalarShiftImm(bool U, u32 immh, u32 immb, u32 opcode, ARM64Reg Rd, ARM64Reg Rn); + void EmitShiftImm(bool Q, bool U, u32 imm, u32 opcode, ARM64Reg Rd, ARM64Reg Rn); + void EmitScalarShiftImm(bool U, u32 imm, u32 opcode, ARM64Reg Rd, ARM64Reg Rn); void EmitLoadStoreMultipleStructure(u32 size, bool L, u32 opcode, ARM64Reg Rt, ARM64Reg Rn); void EmitLoadStoreMultipleStructurePost(u32 size, bool L, u32 opcode, ARM64Reg Rt, ARM64Reg Rn, ARM64Reg Rm);