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https://github.com/dolphin-emu/dolphin.git
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JitArm64: Refactor CR bit manipulation code
This brings JitArm64 more in line with Jit64, and makes the next commit easier to implement. No functional change.
This commit is contained in:
JosJuice
parent
54b37f6bc4
commit
bbe271eec6
@ -355,8 +355,13 @@ protected:
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Arm64Gen::ARM64Reg exit_address_after_return_reg = Arm64Gen::ARM64Reg::INVALID_REG);
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void WriteBLRExit(Arm64Gen::ARM64Reg dest);
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Arm64Gen::FixupBranch JumpIfCRFieldBit(int field, int bit, bool jump_if_set);
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void GetCRFieldBit(int field, int bit, Arm64Gen::ARM64Reg out, bool negate = false);
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void SetCRFieldBit(int field, int bit, Arm64Gen::ARM64Reg in);
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void ClearCRFieldBit(int field, int bit);
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void SetCRFieldBit(int field, int bit);
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void FixGTBeforeSettingCRFieldBit(Arm64Gen::ARM64Reg reg);
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Arm64Gen::FixupBranch JumpIfCRFieldBit(int field, int bit, bool jump_if_set);
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void UpdateFPExceptionSummary(Arm64Gen::ARM64Reg fpscr);
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void UpdateRoundingMode();
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@ -20,6 +20,142 @@
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using namespace Arm64Gen;
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void JitArm64::GetCRFieldBit(int field, int bit, ARM64Reg out, bool negate)
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{
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ARM64Reg CR = gpr.CR(field);
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ARM64Reg WCR = EncodeRegTo32(CR);
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switch (bit)
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{
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case PowerPC::CR_SO_BIT: // check bit 59 set
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UBFX(out, CR, PowerPC::CR_EMU_SO_BIT, 1);
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if (negate)
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EOR(out, out, LogicalImm(1, GPRSize::B64));
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break;
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case PowerPC::CR_EQ_BIT: // check bits 31-0 == 0
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CMP(WCR, ARM64Reg::WZR);
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CSET(out, negate ? CC_NEQ : CC_EQ);
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break;
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case PowerPC::CR_GT_BIT: // check val > 0
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CMP(CR, ARM64Reg::ZR);
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CSET(out, negate ? CC_LE : CC_GT);
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break;
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case PowerPC::CR_LT_BIT: // check bit 62 set
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UBFX(out, CR, PowerPC::CR_EMU_LT_BIT, 1);
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if (negate)
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EOR(out, out, LogicalImm(1, GPRSize::B64));
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break;
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default:
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ASSERT_MSG(DYNA_REC, false, "Invalid CR bit");
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}
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}
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void JitArm64::SetCRFieldBit(int field, int bit, ARM64Reg in)
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{
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gpr.BindCRToRegister(field, true);
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ARM64Reg CR = gpr.CR(field);
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if (bit != PowerPC::CR_GT_BIT)
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FixGTBeforeSettingCRFieldBit(CR);
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switch (bit)
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{
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case PowerPC::CR_SO_BIT: // set bit 59 to input
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BFI(CR, in, PowerPC::CR_EMU_SO_BIT, 1);
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break;
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case PowerPC::CR_EQ_BIT: // clear low 32 bits, set bit 0 to !input
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AND(CR, CR, LogicalImm(0xFFFF'FFFF'0000'0000, GPRSize::B64));
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EOR(in, in, LogicalImm(1, GPRSize::B64));
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ORR(CR, CR, in);
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break;
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case PowerPC::CR_GT_BIT: // set bit 63 to !input
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EOR(in, in, LogicalImm(1, GPRSize::B64));
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BFI(CR, in, 63, 1);
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break;
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case PowerPC::CR_LT_BIT: // set bit 62 to input
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BFI(CR, in, PowerPC::CR_EMU_LT_BIT, 1);
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break;
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}
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ORR(CR, CR, LogicalImm(1ULL << 32, GPRSize::B64));
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}
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void JitArm64::ClearCRFieldBit(int field, int bit)
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{
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gpr.BindCRToRegister(field, true);
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ARM64Reg XA = gpr.CR(field);
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switch (bit)
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{
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case PowerPC::CR_SO_BIT:
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AND(XA, XA, LogicalImm(~(u64(1) << PowerPC::CR_EMU_SO_BIT), GPRSize::B64));
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break;
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case PowerPC::CR_EQ_BIT:
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FixGTBeforeSettingCRFieldBit(XA);
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ORR(XA, XA, LogicalImm(1, GPRSize::B64));
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break;
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case PowerPC::CR_GT_BIT:
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ORR(XA, XA, LogicalImm(u64(1) << 63, GPRSize::B64));
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break;
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case PowerPC::CR_LT_BIT:
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AND(XA, XA, LogicalImm(~(u64(1) << PowerPC::CR_EMU_LT_BIT), GPRSize::B64));
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break;
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}
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}
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void JitArm64::SetCRFieldBit(int field, int bit)
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{
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gpr.BindCRToRegister(field, true);
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ARM64Reg XA = gpr.CR(field);
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if (bit != PowerPC::CR_GT_BIT)
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FixGTBeforeSettingCRFieldBit(XA);
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switch (bit)
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{
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case PowerPC::CR_SO_BIT:
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ORR(XA, XA, LogicalImm(u64(1) << PowerPC::CR_EMU_SO_BIT, GPRSize::B64));
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break;
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case PowerPC::CR_EQ_BIT:
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AND(XA, XA, LogicalImm(0xFFFF'FFFF'0000'0000, GPRSize::B64));
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break;
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case PowerPC::CR_GT_BIT:
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AND(XA, XA, LogicalImm(~(u64(1) << 63), GPRSize::B64));
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break;
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case PowerPC::CR_LT_BIT:
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ORR(XA, XA, LogicalImm(u64(1) << PowerPC::CR_EMU_LT_BIT, GPRSize::B64));
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break;
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}
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ORR(XA, XA, LogicalImm(u64(1) << 32, GPRSize::B64));
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}
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void JitArm64::FixGTBeforeSettingCRFieldBit(ARM64Reg reg)
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{
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// GT is considered unset if the internal representation is <= 0, or in other words,
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// if the internal representation either has bit 63 set or has all bits set to zero.
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// If all bits are zero and we set some bit that's unrelated to GT, we need to set bit 63 so GT
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// doesn't accidentally become considered set. Gross but necessary; this can break actual games.
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auto WA = gpr.GetScopedReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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ORR(XA, reg, LogicalImm(1ULL << 63, GPRSize::B64));
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CMP(reg, ARM64Reg::ZR);
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CSEL(reg, reg, XA, CC_NEQ);
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}
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FixupBranch JitArm64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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{
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ARM64Reg XA = gpr.CR(field);
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@ -42,19 +178,6 @@ FixupBranch JitArm64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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}
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}
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void JitArm64::FixGTBeforeSettingCRFieldBit(Arm64Gen::ARM64Reg reg)
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{
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// GT is considered unset if the internal representation is <= 0, or in other words,
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// if the internal representation either has bit 63 set or has all bits set to zero.
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// If all bits are zero and we set some bit that's unrelated to GT, we need to set bit 63 so GT
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// doesn't accidentally become considered set. Gross but necessary; this can break actual games.
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auto WA = gpr.GetScopedReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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ORR(XA, reg, LogicalImm(1ULL << 63, GPRSize::B64));
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CMP(reg, ARM64Reg::ZR);
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CSEL(reg, reg, XA, CC_NEQ);
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}
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void JitArm64::UpdateFPExceptionSummary(ARM64Reg fpscr)
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{
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auto WA = gpr.GetScopedReg();
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@ -471,67 +594,14 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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// Special case: crclr
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if (inst.CRBA == inst.CRBB && inst.CRBA == inst.CRBD && inst.SUBOP10 == 193)
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{
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// Clear CR field bit
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int field = inst.CRBD >> 2;
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int bit = 3 - (inst.CRBD & 3);
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gpr.BindCRToRegister(field, true);
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ARM64Reg XA = gpr.CR(field);
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switch (bit)
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{
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case PowerPC::CR_SO_BIT:
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AND(XA, XA, LogicalImm(~(u64(1) << PowerPC::CR_EMU_SO_BIT), GPRSize::B64));
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break;
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case PowerPC::CR_EQ_BIT:
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FixGTBeforeSettingCRFieldBit(XA);
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ORR(XA, XA, LogicalImm(1, GPRSize::B64));
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break;
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case PowerPC::CR_GT_BIT:
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ORR(XA, XA, LogicalImm(u64(1) << 63, GPRSize::B64));
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break;
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case PowerPC::CR_LT_BIT:
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AND(XA, XA, LogicalImm(~(u64(1) << PowerPC::CR_EMU_LT_BIT), GPRSize::B64));
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break;
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}
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ClearCRFieldBit(inst.CRBD >> 2, 3 - (inst.CRBD & 3));
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return;
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}
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// Special case: crset
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if (inst.CRBA == inst.CRBB && inst.CRBA == inst.CRBD && inst.SUBOP10 == 289)
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{
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// SetCRFieldBit
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int field = inst.CRBD >> 2;
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int bit = 3 - (inst.CRBD & 3);
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gpr.BindCRToRegister(field, true);
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ARM64Reg XA = gpr.CR(field);
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if (bit != PowerPC::CR_GT_BIT)
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FixGTBeforeSettingCRFieldBit(XA);
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switch (bit)
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{
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case PowerPC::CR_SO_BIT:
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ORR(XA, XA, LogicalImm(u64(1) << PowerPC::CR_EMU_SO_BIT, GPRSize::B64));
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break;
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case PowerPC::CR_EQ_BIT:
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AND(XA, XA, LogicalImm(0xFFFF'FFFF'0000'0000, GPRSize::B64));
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break;
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case PowerPC::CR_GT_BIT:
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AND(XA, XA, LogicalImm(~(u64(1) << 63), GPRSize::B64));
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break;
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case PowerPC::CR_LT_BIT:
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ORR(XA, XA, LogicalImm(u64(1) << PowerPC::CR_EMU_LT_BIT, GPRSize::B64));
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break;
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}
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ORR(XA, XA, LogicalImm(u64(1) << 32, GPRSize::B64));
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SetCRFieldBit(inst.CRBD >> 2, 3 - (inst.CRBD & 3));
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return;
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}
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@ -547,44 +617,8 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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bool negateB =
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inst.SUBOP10 == 129 || inst.SUBOP10 == 417 || inst.SUBOP10 == 225 || inst.SUBOP10 == 33;
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// GetCRFieldBit
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for (int i = 0; i < 2; i++)
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{
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int field = i ? inst.CRBB >> 2 : inst.CRBA >> 2;
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int bit = i ? 3 - (inst.CRBB & 3) : 3 - (inst.CRBA & 3);
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ARM64Reg out = i ? XB : XA;
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bool negate = i ? negateB : negateA;
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ARM64Reg XC = gpr.CR(field);
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ARM64Reg WC = EncodeRegTo32(XC);
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switch (bit)
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{
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case PowerPC::CR_SO_BIT: // check bit 59 set
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UBFX(out, XC, PowerPC::CR_EMU_SO_BIT, 1);
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if (negate)
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EOR(out, out, LogicalImm(1, GPRSize::B64));
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break;
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case PowerPC::CR_EQ_BIT: // check bits 31-0 == 0
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CMP(WC, ARM64Reg::WZR);
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CSET(out, negate ? CC_NEQ : CC_EQ);
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break;
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case PowerPC::CR_GT_BIT: // check val > 0
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CMP(XC, ARM64Reg::ZR);
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CSET(out, negate ? CC_LE : CC_GT);
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break;
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case PowerPC::CR_LT_BIT: // check bit 62 set
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UBFX(out, XC, PowerPC::CR_EMU_LT_BIT, 1);
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if (negate)
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EOR(out, out, LogicalImm(1, GPRSize::B64));
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break;
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default:
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ASSERT_MSG(DYNA_REC, false, "Invalid CR bit");
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}
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}
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GetCRFieldBit(inst.CRBA >> 2, 3 - (inst.CRBA & 3), XA, negateA);
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GetCRFieldBit(inst.CRBB >> 2, 3 - (inst.CRBB & 3), XB, negateB);
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// Compute combined bit
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switch (inst.SUBOP10)
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@ -609,38 +643,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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}
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// Store result bit in CRBD
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int field = inst.CRBD >> 2;
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int bit = 3 - (inst.CRBD & 3);
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gpr.BindCRToRegister(field, true);
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ARM64Reg CR = gpr.CR(field);
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if (bit != PowerPC::CR_GT_BIT)
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FixGTBeforeSettingCRFieldBit(CR);
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switch (bit)
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{
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case PowerPC::CR_SO_BIT: // set bit 59 to input
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BFI(CR, XA, PowerPC::CR_EMU_SO_BIT, 1);
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break;
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case PowerPC::CR_EQ_BIT: // clear low 32 bits, set bit 0 to !input
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AND(CR, CR, LogicalImm(0xFFFF'FFFF'0000'0000, GPRSize::B64));
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EOR(XA, XA, LogicalImm(1, GPRSize::B64));
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ORR(CR, CR, XA);
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break;
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case PowerPC::CR_GT_BIT: // set bit 63 to !input
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EOR(XA, XA, LogicalImm(1, GPRSize::B64));
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BFI(CR, XA, 63, 1);
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break;
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case PowerPC::CR_LT_BIT: // set bit 62 to input
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BFI(CR, XA, PowerPC::CR_EMU_LT_BIT, 1);
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break;
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}
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ORR(CR, CR, LogicalImm(1ULL << 32, GPRSize::B64));
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SetCRFieldBit(inst.CRBD >> 2, 3 - (inst.CRBD & 3), XA);
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}
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void JitArm64::mfcr(UGeckoInstruction inst)
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