x64Emitter: Refactor OpArg::WriteRest

Shorter, displacement is now handled in one location.
This commit is contained in:
Sintendo 2020-01-13 00:10:46 +01:00
parent cde3a3b448
commit bdfc472751

View File

@ -270,52 +270,27 @@ void OpArg::WriteRest(XEmitter* emit, int extraBytes, X64Reg _operandReg,
return; return;
} }
if (scale == 0) if (scale == SCALE_NONE)
{ {
// Oh, no memory, Just a reg. // Oh, no memory, Just a reg.
mod = 3; // 11 mod = 3; // 11
} }
else
{
// Ah good, no scaling.
if (scale == SCALE_ATREG && !((_offsetOrBaseReg & 7) == 4 || (_offsetOrBaseReg & 7) == 5))
{
// Okay, we're good. No SIB necessary.
int ioff = (int)offset;
if (ioff == 0)
{
mod = 0;
}
else if (ioff < -128 || ioff > 127)
{
mod = 2; // 32-bit displacement
}
else
{
mod = 1; // 8-bit displacement
}
}
else if (scale >= SCALE_NOBASE_2 && scale <= SCALE_NOBASE_8) else if (scale >= SCALE_NOBASE_2 && scale <= SCALE_NOBASE_8)
{ {
SIB = true; SIB = true;
mod = 0; mod = 0;
_offsetOrBaseReg = 5; _offsetOrBaseReg = 5;
// Always has 32-bit displacement
} }
else else
{ {
if ((_offsetOrBaseReg & 7) == 4) // this would occupy the SIB encoding :( if (scale != SCALE_ATREG)
{
// So we have to fake it with SIB encoding :(
SIB = true;
}
if (scale >= SCALE_1 && scale < SCALE_ATREG)
{ {
SIB = true; SIB = true;
} }
else if ((_offsetOrBaseReg & 7) == 4)
if (scale == SCALE_ATREG && ((_offsetOrBaseReg & 7) == 4))
{ {
// Special case for which SCALE_ATREG needs SIB
SIB = true; SIB = true;
ireg = _offsetOrBaseReg; ireg = _offsetOrBaseReg;
} }
@ -325,16 +300,15 @@ void OpArg::WriteRest(XEmitter* emit, int extraBytes, X64Reg _operandReg,
int ioff = (int)(s64)offset; int ioff = (int)(s64)offset;
if (ioff == 0 && (_offsetOrBaseReg & 7) != 5) if (ioff == 0 && (_offsetOrBaseReg & 7) != 5)
{ {
mod = 0; mod = 0; // No displacement
} }
else if (ioff < -128 || ioff > 127) else if (ioff >= -128 && ioff <= 127)
{
mod = 2; // 32-bit displacement
}
else
{ {
mod = 1; // 8-bit displacement mod = 1; // 8-bit displacement
} }
else
{
mod = 2; // 32-bit displacement
} }
} }