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JitArm64: Fix register number typo

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I think this typo was actually ignored by the code, but nevertheless,
it should be fixed.
This commit is contained in:
JosJuice 2022-10-06 23:04:44 +02:00
parent 04628034bc
commit bf492c1ff3
1 changed files with 1 additions and 1 deletions
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Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
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@ -314,7 +314,7 @@ void JitArm64::GenerateFrsqrte()
LSR(ARM64Reg::X2, ARM64Reg::X2, 48);
AND(ARM64Reg::X2, ARM64Reg::X2, LogicalImm(0x10, 64));
MOVP2R(ARM64Reg::X1, &Common::frsqrte_expected);
ORR(ARM64Reg::X2, ARM64Reg::X2, ARM64Reg::X3, ArithOption(ARM64Reg::X8, ShiftType::LSR, 48));
ORR(ARM64Reg::X2, ARM64Reg::X2, ARM64Reg::X3, ArithOption(ARM64Reg::X3, ShiftType::LSR, 48));
EOR(ARM64Reg::X2, ARM64Reg::X2, LogicalImm(0x10, 64));
ADD(ARM64Reg::X2, ARM64Reg::X1, ARM64Reg::X2, ArithOption(ARM64Reg::X2, ShiftType::LSL, 3));
LDP(IndexType::Signed, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::X2, 0);