diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.h b/Source/Core/Core/PowerPC/JitArm64/Jit.h
index 7ad9464e05..a15712d36f 100644
--- a/Source/Core/Core/PowerPC/JitArm64/Jit.h
+++ b/Source/Core/Core/PowerPC/JitArm64/Jit.h
@@ -137,56 +137,20 @@ public:
 	void stfXX(UGeckoInstruction inst);
 
 	// Floating point
-	void fabsx(UGeckoInstruction inst);
-	void faddsx(UGeckoInstruction inst);
-	void faddx(UGeckoInstruction inst);
-	void fmaddsx(UGeckoInstruction inst);
-	void fmaddx(UGeckoInstruction inst);
-	void fmrx(UGeckoInstruction inst);
-	void fmsubsx(UGeckoInstruction inst);
-	void fmsubx(UGeckoInstruction inst);
-	void fmulsx(UGeckoInstruction inst);
-	void fmulx(UGeckoInstruction inst);
-	void fnabsx(UGeckoInstruction inst);
-	void fnegx(UGeckoInstruction inst);
-	void fnmaddsx(UGeckoInstruction inst);
-	void fnmaddx(UGeckoInstruction inst);
-	void fnmsubsx(UGeckoInstruction inst);
-	void fnmsubx(UGeckoInstruction inst);
+	void fp_arith(UGeckoInstruction inst);
+	void fp_logic(UGeckoInstruction inst);
 	void fselx(UGeckoInstruction inst);
-	void fsubsx(UGeckoInstruction inst);
-	void fsubx(UGeckoInstruction inst);
 	void fcmpX(UGeckoInstruction inst);
 	void frspx(UGeckoInstruction inst);
 	void fctiwzx(UGeckoInstruction inst);
-	void fdivx(UGeckoInstruction inst);
-	void fdivsx(UGeckoInstruction inst);
 
 	// Paired
-	void ps_abs(UGeckoInstruction inst);
-	void ps_add(UGeckoInstruction inst);
-	void ps_div(UGeckoInstruction inst);
-	void ps_madd(UGeckoInstruction inst);
-	void ps_madds0(UGeckoInstruction inst);
-	void ps_madds1(UGeckoInstruction inst);
-	void ps_merge00(UGeckoInstruction inst);
-	void ps_merge01(UGeckoInstruction inst);
-	void ps_merge10(UGeckoInstruction inst);
-	void ps_merge11(UGeckoInstruction inst);
-	void ps_mr(UGeckoInstruction inst);
-	void ps_msub(UGeckoInstruction inst);
-	void ps_mul(UGeckoInstruction inst);
-	void ps_muls0(UGeckoInstruction inst);
-	void ps_muls1(UGeckoInstruction inst);
-	void ps_nabs(UGeckoInstruction inst);
-	void ps_nmadd(UGeckoInstruction inst);
-	void ps_nmsub(UGeckoInstruction inst);
-	void ps_neg(UGeckoInstruction inst);
+	void ps_maddXX(UGeckoInstruction inst);
+	void ps_mergeXX(UGeckoInstruction inst);
+	void ps_mulsX(UGeckoInstruction inst);
 	void ps_res(UGeckoInstruction inst);
 	void ps_sel(UGeckoInstruction inst);
-	void ps_sub(UGeckoInstruction inst);
-	void ps_sum0(UGeckoInstruction inst);
-	void ps_sum1(UGeckoInstruction inst);
+	void ps_sumX(UGeckoInstruction inst);
 
 	// Loadstore paired
 	void psq_l(UGeckoInstruction inst);
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
index 5ad2bf8321..f1f956db69 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
@@ -17,284 +17,114 @@
 
 using namespace Arm64Gen;
 
-void JitArm64::fabsx(UGeckoInstruction inst)
+void JitArm64::fp_arith(UGeckoInstruction inst)
+{
+	INSTRUCTION_START
+	JITDISABLE(bJITFloatingPointOff);
+	FALLBACK_IF(inst.Rc);
+	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
+
+	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
+	u32 op5 = inst.SUBOP5;
+
+	bool single = inst.OPCD == 59;
+	bool packed = inst.OPCD == 4;
+
+	bool use_c = op5 >= 25; // fmul and all kind of fmaddXX
+	bool use_b = op5 != 25; // fmul uses no B
+
+	ARM64Reg VA, VB, VC, VD;
+
+	if (packed)
+	{
+		VA = fpr.R(a, REG_REG);
+		if (use_b)
+			VB = fpr.R(b, REG_REG);
+		if (use_c)
+			VC = fpr.R(c, REG_REG);
+		VD = fpr.RW(d, REG_REG);
+
+		switch (op5)
+		{
+		case 18: m_float_emit.FDIV(64, VD, VA, VB); break;
+		case 20: m_float_emit.FSUB(64, VD, VA, VB); break;
+		case 21: m_float_emit.FADD(64, VD, VA, VB); break;
+		case 25: m_float_emit.FMUL(64, VD, VA, VC); break;
+		default: _assert_msg_(DYNA_REC, 0, "fp_arith"); break;
+		}
+	}
+	else
+	{
+		VA = EncodeRegToDouble(fpr.R(a, REG_IS_LOADED));
+		if (use_b)
+			VB = EncodeRegToDouble(fpr.R(b, REG_IS_LOADED));
+		if (use_c)
+			VC = EncodeRegToDouble(fpr.R(c, REG_IS_LOADED));
+		VD = EncodeRegToDouble(fpr.RW(d, single ? REG_DUP : REG_LOWER_PAIR));
+
+		switch (op5)
+		{
+		case 18: m_float_emit.FDIV(VD, VA, VB); break;
+		case 20: m_float_emit.FSUB(VD, VA, VB); break;
+		case 21: m_float_emit.FADD(VD, VA, VB); break;
+		case 25: m_float_emit.FMUL(VD, VA, VC); break;
+		case 28: m_float_emit.FNMSUB(VD, VA, VC, VB); break; // fmsub: "D = A*C - B" vs "Vd = (-Va) + Vn*Vm"
+		case 29: m_float_emit.FMADD(VD, VA, VC, VB); break; // fmadd: "D = A*C + B" vs "Vd = Va + Vn*Vm"
+		case 30: m_float_emit.FMSUB(VD, VA, VC, VB); break; // fnmsub: "D = -(A*C - B)" vs "Vd = Va + (-Vn)*Vm"
+		case 31: m_float_emit.FNMADD(VD, VA, VC, VB); break; // fnmadd: "D = -(A*C + B)" vs "Vd = (-Va) + (-Vn)*Vm"
+		default: _assert_msg_(DYNA_REC, 0, "fp_arith"); break;
+		}
+	}
+
+	if (single || packed)
+		fpr.FixSinglePrecision(d);
+}
+
+void JitArm64::fp_logic(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITFloatingPointOff);
 	FALLBACK_IF(inst.Rc);
 
 	u32 b = inst.FB, d = inst.FD;
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB));
-}
-
-void JitArm64::faddsx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d, REG_DUP);
-
-	m_float_emit.FADD(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VB));
-	fpr.FixSinglePrecision(d);
-}
-
-void JitArm64::faddx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.FADD(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VB));
-}
-
-void JitArm64::fmaddsx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d, REG_DUP);
-	ARM64Reg V0 = fpr.GetReg();
-
-	m_float_emit.FMUL(EncodeRegToDouble(V0), EncodeRegToDouble(VA), EncodeRegToDouble(VC));
-	m_float_emit.FADD(EncodeRegToDouble(VD), EncodeRegToDouble(V0), EncodeRegToDouble(VB));
-	fpr.FixSinglePrecision(d);
-
-	fpr.Unlock(V0);
-}
-
-void JitArm64::fmaddx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.FMADD(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VC), EncodeRegToDouble(VB));
-}
-
-void JitArm64::fmrx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
-
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.INS(64, VD, 0, VB, 0);
-}
-
-void JitArm64::fmsubsx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d, REG_DUP);
-	ARM64Reg V0 = fpr.GetReg();
-
-	m_float_emit.FMUL(EncodeRegToDouble(V0), EncodeRegToDouble(VA), EncodeRegToDouble(VC));
-	m_float_emit.FSUB(EncodeRegToDouble(VD), EncodeRegToDouble(V0), EncodeRegToDouble(VB));
-	fpr.FixSinglePrecision(d);
-
-	fpr.Unlock(V0);
-}
-
-void JitArm64::fmsubx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.FNMSUB(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VC), EncodeRegToDouble(VB));
-}
-
-void JitArm64::fmulsx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d, REG_DUP);
-
-	m_float_emit.FMUL(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VC));
-	fpr.FixSinglePrecision(d);
-}
-
-void JitArm64::fmulx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.FMUL(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VC));
-}
-
-void JitArm64::fnabsx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
-
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB));
-	m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VD));
-}
-
-void JitArm64::fnegx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
-
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VB));
-}
-
-void JitArm64::fnmaddsx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d, REG_DUP);
-	ARM64Reg V0 = fpr.GetReg();
-
-	m_float_emit.FMUL(EncodeRegToDouble(V0), EncodeRegToDouble(VA), EncodeRegToDouble(VC));
-	m_float_emit.FADD(EncodeRegToDouble(VD), EncodeRegToDouble(V0), EncodeRegToDouble(VB));
-	m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VD));
-	fpr.FixSinglePrecision(d);
-
-	fpr.Unlock(V0);
-}
-
-void JitArm64::fnmaddx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.FNMADD(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VC), EncodeRegToDouble(VB));
-}
-
-void JitArm64::fnmsubsx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d, REG_DUP);
-	ARM64Reg V0 = fpr.GetReg();
-
-	m_float_emit.FMUL(EncodeRegToDouble(V0), EncodeRegToDouble(VA), EncodeRegToDouble(VC));
-	m_float_emit.FSUB(EncodeRegToDouble(VD), EncodeRegToDouble(V0), EncodeRegToDouble(VB));
-	m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VD));
-	fpr.FixSinglePrecision(d);
-
-	fpr.Unlock(V0);
-}
-
-void JitArm64::fnmsubx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.FMSUB(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VC), EncodeRegToDouble(VB));
+	u32 op10 = inst.SUBOP10;
+
+	bool packed = inst.OPCD == 4;
+
+	// MR with source === dest => no-op
+	if (op10 == 72 && b == d)
+		return;
+
+	if (packed)
+	{
+		ARM64Reg VB = fpr.R(b, REG_REG);
+		ARM64Reg VD = fpr.RW(d, REG_REG);
+
+		switch (op10)
+		{
+		case  40: m_float_emit.FNEG(64, VD, VB); break;
+		case  72: m_float_emit.ORR(VD, VB, VB); break;
+		case 136: m_float_emit.FABS(64, VD, VB);
+		          m_float_emit.FNEG(64, VD, VD); break;
+		case 264: m_float_emit.FABS(64, VD, VB); break;
+		default: _assert_msg_(DYNA_REC, 0, "fp_logic"); break;
+		}
+	}
+	else
+	{
+		ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
+		ARM64Reg VD = fpr.RW(d);
+
+		switch (op10)
+		{
+		case  40: m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VB)); break;
+		case  72: m_float_emit.INS(64, VD, 0, VB, 0); break;
+		case 136: m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB));
+		          m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VD)); break;
+		case 264: m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB)); break;
+		default: _assert_msg_(DYNA_REC, 0, "fp_logic"); break;
+		}
+	}
 }
 
 void JitArm64::fselx(UGeckoInstruction inst)
@@ -314,39 +144,6 @@ void JitArm64::fselx(UGeckoInstruction inst)
 	m_float_emit.FCSEL(EncodeRegToDouble(VD), EncodeRegToDouble(VC), EncodeRegToDouble(VB), CC_GE);
 }
 
-void JitArm64::fsubsx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d, REG_DUP);
-
-	m_float_emit.FSUB(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VB));
-	fpr.FixSinglePrecision(d);
-}
-
-void JitArm64::fsubx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.FSUB(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VB));
-}
-
 void JitArm64::frspx(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
@@ -448,36 +245,3 @@ void JitArm64::fctiwzx(UGeckoInstruction inst)
 	m_float_emit.ORR(EncodeRegToDouble(VD), EncodeRegToDouble(VD), EncodeRegToDouble(V0));
 	fpr.Unlock(V0);
 }
-
-void JitArm64::fdivx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.FDIV(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VB));
-}
-
-void JitArm64::fdivsx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d, REG_DUP);
-
-	m_float_emit.FDIV(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VB));
-	fpr.FixSinglePrecision(d);
-}
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp
index 8b774978cd..c17c22b549 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp
@@ -17,123 +17,7 @@
 
 using namespace Arm64Gen;
 
-void JitArm64::ps_abs(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
-
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.FABS(64, VD, VB);
-}
-
-void JitArm64::ps_add(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.FADD(64, VD, VA, VB);
-	fpr.FixSinglePrecision(d);
-}
-
-void JitArm64::ps_div(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.FDIV(64, VD, VA, VB);
-	fpr.FixSinglePrecision(d);
-}
-
-void JitArm64::ps_madd(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-	ARM64Reg V0 = fpr.GetReg();
-
-	m_float_emit.FMUL(64, V0, VA, VC);
-	m_float_emit.FADD(64, VD, V0, VB);
-	fpr.FixSinglePrecision(d);
-
-	fpr.Unlock(V0);
-}
-
-void JitArm64::ps_madds0(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-	ARM64Reg V0 = fpr.GetReg();
-
-	m_float_emit.DUP(64, V0, VC, 0);
-	m_float_emit.FMUL(64, V0, V0, VA);
-	m_float_emit.FADD(64, VD, V0, VB);
-	fpr.FixSinglePrecision(d);
-
-	fpr.Unlock(V0);
-}
-
-void JitArm64::ps_madds1(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-	ARM64Reg V0 = fpr.GetReg();
-
-	m_float_emit.DUP(64, V0, VC, 1);
-	m_float_emit.FMUL(64, V0, V0, VA);
-	m_float_emit.FADD(64, VD, V0, VB);
-	fpr.FixSinglePrecision(d);
-
-	fpr.Unlock(V0);
-}
-
-void JitArm64::ps_merge00(UGeckoInstruction inst)
+void JitArm64::ps_mergeXX(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITPairedOff);
@@ -145,85 +29,40 @@ void JitArm64::ps_merge00(UGeckoInstruction inst)
 	ARM64Reg VB = fpr.R(b, REG_REG);
 	ARM64Reg VD = fpr.RW(d, REG_REG);
 
-	m_float_emit.TRN1(64, VD, VA, VB);
-}
-
-void JitArm64::ps_merge01(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.INS(64, VD, 0, VA, 0);
-	m_float_emit.INS(64, VD, 1, VB, 1);
-}
-
-void JitArm64::ps_merge10(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	if (d != a && d != b)
+	switch (inst.SUBOP10)
 	{
-		m_float_emit.INS(64, VD, 0, VA, 1);
-		m_float_emit.INS(64, VD, 1, VB, 0);
-	}
-	else
-	{
-		ARM64Reg V0 = fpr.GetReg();
-		m_float_emit.INS(64, V0, 0, VA, 1);
-		m_float_emit.INS(64, V0, 1, VB, 0);
-		m_float_emit.ORR(VD, V0, V0);
-		fpr.Unlock(V0);
+	case 528: //00
+		m_float_emit.TRN1(64, VD, VA, VB);
+		break;
+	case 560: //01
+		m_float_emit.INS(64, VD, 0, VA, 0);
+		m_float_emit.INS(64, VD, 1, VB, 1);
+		break;
+	case 592: //10
+		if (d != a && d != b)
+		{
+			m_float_emit.INS(64, VD, 0, VA, 1);
+			m_float_emit.INS(64, VD, 1, VB, 0);
+		}
+		else
+		{
+			ARM64Reg V0 = fpr.GetReg();
+			m_float_emit.INS(64, V0, 0, VA, 1);
+			m_float_emit.INS(64, V0, 1, VB, 0);
+			m_float_emit.ORR(VD, V0, V0);
+			fpr.Unlock(V0);
+		}
+		break;
+	case 624: //11
+		m_float_emit.TRN2(64, VD, VA, VB);
+		break;
+	default:
+		_assert_msg_(DYNA_REC, 0, "ps_merge - invalid op");
+		break;
 	}
 }
 
-void JitArm64::ps_merge11(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.TRN2(64, VD, VA, VB);
-}
-
-void JitArm64::ps_mr(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
-
-	if (d == b)
-		return;
-
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.ORR(VD, VB, VB);
-}
-
-void JitArm64::ps_mul(UGeckoInstruction inst)
+void JitArm64::ps_mulsX(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITPairedOff);
@@ -232,55 +71,20 @@ void JitArm64::ps_mul(UGeckoInstruction inst)
 
 	u32 a = inst.FA, c = inst.FC, d = inst.FD;
 
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.FMUL(64, VD, VA, VC);
-	fpr.FixSinglePrecision(d);
-}
-
-void JitArm64::ps_muls0(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, c = inst.FC, d = inst.FD;
+	bool upper = inst.SUBOP5 == 13;
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VC = fpr.R(c, REG_REG);
 	ARM64Reg VD = fpr.RW(d, REG_REG);
 	ARM64Reg V0 = fpr.GetReg();
 
-	m_float_emit.DUP(64, V0, VC, 0);
+	m_float_emit.DUP(64, V0, VC, upper ? 1 : 0);
 	m_float_emit.FMUL(64, VD, VA, V0);
 	fpr.FixSinglePrecision(d);
 	fpr.Unlock(V0);
 }
 
-void JitArm64::ps_muls1(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-	ARM64Reg V0 = fpr.GetReg();
-
-	m_float_emit.DUP(64, V0, VC, 1);
-	m_float_emit.FMUL(64, VD, VA, V0);
-	fpr.FixSinglePrecision(d);
-	fpr.Unlock(V0);
-}
-
-void JitArm64::ps_msub(UGeckoInstruction inst)
+void JitArm64::ps_maddXX(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITPairedOff);
@@ -288,6 +92,7 @@ void JitArm64::ps_msub(UGeckoInstruction inst)
 	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
+	u32 op5 = inst.SUBOP5;
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
@@ -295,83 +100,40 @@ void JitArm64::ps_msub(UGeckoInstruction inst)
 	ARM64Reg VD = fpr.RW(d, REG_REG);
 	ARM64Reg V0 = fpr.GetReg();
 
-	m_float_emit.FMUL(64, V0, VA, VC);
-	m_float_emit.FSUB(64, VD, V0, VB);
-	fpr.FixSinglePrecision(d);
-
-	fpr.Unlock(V0);
-}
-
-void JitArm64::ps_nabs(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
-
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.FABS(64, VD, VB);
-	m_float_emit.FNEG(64, VD, VD);
-}
-
-void JitArm64::ps_neg(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
-
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.FNEG(64, VD, VB);
-}
-
-void JitArm64::ps_nmadd(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-	ARM64Reg V0 = fpr.GetReg();
-
-	m_float_emit.FMUL(64, V0, VA, VC);
-	m_float_emit.FADD(64, VD, V0, VB);
-	m_float_emit.FNEG(64, VD, VD);
-	fpr.FixSinglePrecision(d);
-
-	fpr.Unlock(V0);
-}
-
-void JitArm64::ps_nmsub(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-	ARM64Reg V0 = fpr.GetReg();
-
-	m_float_emit.FMUL(64, V0, VA, VC);
-	m_float_emit.FSUB(64, VD, V0, VB);
-	m_float_emit.FNEG(64, VD, VD);
+	switch (op5)
+	{
+	case 14: // ps_madds0
+		m_float_emit.DUP(64, V0, VC, 0);
+		m_float_emit.FMUL(64, V0, V0, VA);
+		m_float_emit.FADD(64, VD, V0, VB);
+		break;
+	case 15: // ps_madds1
+		m_float_emit.DUP(64, V0, VC, 1);
+		m_float_emit.FMUL(64, V0, V0, VA);
+		m_float_emit.FADD(64, VD, V0, VB);
+		break;
+	case 28: // ps_msub
+		m_float_emit.FMUL(64, V0, VA, VC);
+		m_float_emit.FSUB(64, VD, V0, VB);
+		break;
+	case 29: // ps_madd
+		m_float_emit.FMUL(64, V0, VA, VC);
+		m_float_emit.FADD(64, VD, V0, VB);
+		break;
+	case 30: // ps_nmsub
+		m_float_emit.FMUL(64, V0, VA, VC);
+		m_float_emit.FSUB(64, VD, V0, VB);
+		m_float_emit.FNEG(64, VD, VD);
+		break;
+	case 31: // ps_nmadd
+		m_float_emit.FMUL(64, V0, VA, VC);
+		m_float_emit.FADD(64, VD, V0, VB);
+		m_float_emit.FNEG(64, VD, VD);
+		break;
+	default:
+		_assert_msg_(DYNA_REC, 0, "ps_madd - invalid op");
+		break;
+	}
 	fpr.FixSinglePrecision(d);
 
 	fpr.Unlock(V0);
@@ -421,24 +183,7 @@ void JitArm64::ps_sel(UGeckoInstruction inst)
 	}
 }
 
-void JitArm64::ps_sub(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.FSUB(64, VD, VA, VB);
-	fpr.FixSinglePrecision(d);
-}
-
-void JitArm64::ps_sum0(UGeckoInstruction inst)
+void JitArm64::ps_sumX(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITPairedOff);
@@ -447,36 +192,7 @@ void JitArm64::ps_sum0(UGeckoInstruction inst)
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
 
-	ARM64Reg VA = fpr.R(a, REG_REG);
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-	ARM64Reg V0 = fpr.GetReg();
-
-	m_float_emit.DUP(64, V0, VB, 1);
-	if (d != c)
-	{
-		m_float_emit.FADD(64, VD, V0, VA);
-		m_float_emit.INS(64, VD, 1, VC, 1);
-	}
-	else
-	{
-		m_float_emit.FADD(64, V0, V0, VA);
-		m_float_emit.INS(64, VD, 0, V0, 0);
-	}
-	fpr.FixSinglePrecision(d);
-
-	fpr.Unlock(V0);
-}
-
-void JitArm64::ps_sum1(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-	FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
-
-	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
+	bool upper = inst.SUBOP5 == 11;
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
@@ -484,16 +200,16 @@ void JitArm64::ps_sum1(UGeckoInstruction inst)
 	ARM64Reg VD = fpr.RW(d, REG_REG);
 	ARM64Reg V0 = fpr.GetReg();
 
-	m_float_emit.DUP(64, V0, VA, 0);
+	m_float_emit.DUP(64, V0, upper ? VA : VB, upper ? 0 : 1);
 	if (d != c)
 	{
-		m_float_emit.FADD(64, VD, V0, VB);
-		m_float_emit.INS(64, VD, 0, VC, 0);
+		m_float_emit.FADD(64, VD, V0, upper ? VB : VA);
+		m_float_emit.INS(64, VD, upper ? 0 : 1, VC, upper ? 0 : 1);
 	}
 	else
 	{
-		m_float_emit.FADD(64, V0, V0, VB);
-		m_float_emit.INS(64, VD, 1, V0, 1);
+		m_float_emit.FADD(64, V0, V0, upper ? VB : VA);
+		m_float_emit.INS(64, VD, upper ? 1 : 0, V0, upper ? 1 : 0);
 	}
 	fpr.FixSinglePrecision(d);
 
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
index af5bc38481..700cf42df9 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
@@ -104,39 +104,39 @@ static GekkoOPTemplate table4[] =
 {    //SUBOP10
 	{0,    &JitArm64::FallBackToInterpreter},   // ps_cmpu0
 	{32,   &JitArm64::FallBackToInterpreter},   // ps_cmpo0
-	{40,   &JitArm64::ps_neg},                  // ps_neg
-	{136,  &JitArm64::ps_nabs},                 // ps_nabs
-	{264,  &JitArm64::ps_abs},                  // ps_abs
+	{40,   &JitArm64::fp_logic},                // ps_neg
+	{136,  &JitArm64::fp_logic},                // ps_nabs
+	{264,  &JitArm64::fp_logic},                // ps_abs
 	{64,   &JitArm64::FallBackToInterpreter},   // ps_cmpu1
-	{72,   &JitArm64::ps_mr},                   // ps_mr
+	{72,   &JitArm64::fp_logic},                // ps_mr
 	{96,   &JitArm64::FallBackToInterpreter},   // ps_cmpo1
-	{528,  &JitArm64::ps_merge00},              // ps_merge00
-	{560,  &JitArm64::ps_merge01},              // ps_merge01
-	{592,  &JitArm64::ps_merge10},              // ps_merge10
-	{624,  &JitArm64::ps_merge11},              // ps_merge11
+	{528,  &JitArm64::ps_mergeXX},              // ps_merge00
+	{560,  &JitArm64::ps_mergeXX},              // ps_merge01
+	{592,  &JitArm64::ps_mergeXX},              // ps_merge10
+	{624,  &JitArm64::ps_mergeXX},              // ps_merge11
 
 	{1014, &JitArm64::FallBackToInterpreter},   // dcbz_l
 };
 
 static GekkoOPTemplate table4_2[] =
 {
-	{10, &JitArm64::ps_sum0},                   // ps_sum0
-	{11, &JitArm64::ps_sum1},                   // ps_sum1
-	{12, &JitArm64::ps_muls0},                  // ps_muls0
-	{13, &JitArm64::ps_muls1},                  // ps_muls1
-	{14, &JitArm64::ps_madds0},                 // ps_madds0
-	{15, &JitArm64::ps_madds1},                 // ps_madds1
-	{18, &JitArm64::ps_div},                    // ps_div
-	{20, &JitArm64::ps_sub},                    // ps_sub
-	{21, &JitArm64::ps_add},                    // ps_add
+	{10, &JitArm64::ps_sumX},                   // ps_sum0
+	{11, &JitArm64::ps_sumX},                   // ps_sum1
+	{12, &JitArm64::ps_mulsX},                  // ps_muls0
+	{13, &JitArm64::ps_mulsX},                  // ps_muls1
+	{14, &JitArm64::ps_maddXX},                 // ps_madds0
+	{15, &JitArm64::ps_maddXX},                 // ps_madds1
+	{18, &JitArm64::fp_arith},                  // ps_div
+	{20, &JitArm64::fp_arith},                  // ps_sub
+	{21, &JitArm64::fp_arith},                  // ps_add
 	{23, &JitArm64::ps_sel},                    // ps_sel
 	{24, &JitArm64::ps_res},                    // ps_res
-	{25, &JitArm64::ps_mul},                    // ps_mul
+	{25, &JitArm64::fp_arith},                  // ps_mul
 	{26, &JitArm64::FallBackToInterpreter},     // ps_rsqrte
-	{28, &JitArm64::ps_msub},                   // ps_msub
-	{29, &JitArm64::ps_madd},                   // ps_madd
-	{30, &JitArm64::ps_nmsub},                  // ps_nmsub
-	{31, &JitArm64::ps_nmadd},                  // ps_nmadd
+	{28, &JitArm64::ps_maddXX},                 // ps_msub
+	{29, &JitArm64::ps_maddXX},                 // ps_madd
+	{30, &JitArm64::ps_maddXX},                 // ps_nmsub
+	{31, &JitArm64::ps_maddXX},                 // ps_nmadd
 };
 
 
@@ -313,27 +313,27 @@ static GekkoOPTemplate table31[] =
 
 static GekkoOPTemplate table59[] =
 {
-	{18, &JitArm64::fdivsx},                    // fdivsx
-	{20, &JitArm64::fsubsx},                    // fsubsx
-	{21, &JitArm64::faddsx},                    // faddsx
+	{18, &JitArm64::fp_arith},                  // fdivsx
+	{20, &JitArm64::fp_arith},                  // fsubsx
+	{21, &JitArm64::fp_arith},                  // faddsx
 	{24, &JitArm64::FallBackToInterpreter},     // fresx
-	{25, &JitArm64::fmulsx},                    // fmulsx
-	{28, &JitArm64::fmsubsx},                   // fmsubsx
-	{29, &JitArm64::fmaddsx},                   // fmaddsx
-	{30, &JitArm64::fnmsubsx},                  // fnmsubsx
-	{31, &JitArm64::fnmaddsx},                  // fnmaddsx
+	{25, &JitArm64::fp_arith},                  // fmulsx
+	{28, &JitArm64::fp_arith},                  // fmsubsx
+	{29, &JitArm64::fp_arith},                  // fmaddsx
+	{30, &JitArm64::fp_arith},                  // fnmsubsx
+	{31, &JitArm64::fp_arith},                  // fnmaddsx
 };
 
 static GekkoOPTemplate table63[] =
 {
-	{264, &JitArm64::fabsx},                    // fabsx
+	{264, &JitArm64::fp_logic},                 // fabsx
 	{32,  &JitArm64::fcmpX},                    // fcmpo
 	{0,   &JitArm64::fcmpX},                    // fcmpu
 	{14,  &JitArm64::FallBackToInterpreter},    // fctiwx
 	{15,  &JitArm64::fctiwzx},                  // fctiwzx
-	{72,  &JitArm64::fmrx},                     // fmrx
-	{136, &JitArm64::fnabsx},                   // fnabsx
-	{40,  &JitArm64::fnegx},                    // fnegx
+	{72,  &JitArm64::fp_logic},                 // fmrx
+	{136, &JitArm64::fp_logic},                 // fnabsx
+	{40,  &JitArm64::fp_logic},                 // fnegx
 	{12,  &JitArm64::frspx},                    // frspx
 
 	{64,  &JitArm64::FallBackToInterpreter},    // mcrfs
@@ -346,16 +346,16 @@ static GekkoOPTemplate table63[] =
 
 static GekkoOPTemplate table63_2[] =
 {
-	{18, &JitArm64::fdivx},                     // fdivx
-	{20, &JitArm64::fsubx},                     // fsubx
-	{21, &JitArm64::faddx},                     // faddx
+	{18, &JitArm64::fp_arith},                  // fdivx
+	{20, &JitArm64::fp_arith},                  // fsubx
+	{21, &JitArm64::fp_arith},                  // faddx
 	{23, &JitArm64::fselx},                     // fselx
-	{25, &JitArm64::fmulx},                     // fmulx
+	{25, &JitArm64::fp_arith},                  // fmulx
 	{26, &JitArm64::FallBackToInterpreter},     // frsqrtex
-	{28, &JitArm64::fmsubx},                    // fmsubx
-	{29, &JitArm64::fmaddx},                    // fmaddx
-	{30, &JitArm64::fnmsubx},                   // fnmsubx
-	{31, &JitArm64::fnmaddx},                   // fnmaddx
+	{28, &JitArm64::fp_arith},                  // fmsubx
+	{29, &JitArm64::fp_arith},                  // fmaddx
+	{30, &JitArm64::fp_arith},                  // fnmsubx
+	{31, &JitArm64::fp_arith},                  // fnmaddx
 };