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Merge pull request #10749 from tellowkrinkle/IntelUbershaders

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VideoCommon: Fix ubershaders on MoltenVK Intel
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JMC47 2022-07-10 19:35:55 -04:00 committed by GitHub
commit cce6133ef6
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4 changed files with 19 additions and 16 deletions
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4
Source/Core/VideoBackends/Vulkan/VulkanContext.cpp
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@ -377,6 +377,10 @@ void VulkanContext::PopulateBackendInfoFeatures(VideoConfig* config, VkPhysicalD
// We will use shader blending, so disable hardware dual source blending. // We will use shader blending, so disable hardware dual source blending.
config->backend_info.bSupportsDualSourceBlend = false; config->backend_info.bSupportsDualSourceBlend = false;
} }
// Dynamic sampler indexing locks up Intel GPUs on MoltenVK/Metal
if (DriverDetails::HasBug(DriverDetails::BUG_BROKEN_DYNAMIC_SAMPLER_INDEXING))
config->backend_info.bSupportsDynamicSamplerIndexing = false;
} }
void VulkanContext::PopulateBackendInfoMultisampleModes( void VulkanContext::PopulateBackendInfoMultisampleModes(

2
Source/Core/VideoCommon/DriverDetails.cpp
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@ -140,6 +140,8 @@ constexpr BugInfo m_known_bugs[] = {
-1.0, -1.0, true}, -1.0, -1.0, true},
{API_VULKAN, OS_OSX, VENDOR_APPLE, DRIVER_PORTABILITY, Family::UNKNOWN, {API_VULKAN, OS_OSX, VENDOR_APPLE, DRIVER_PORTABILITY, Family::UNKNOWN,
BUG_BROKEN_DISCARD_WITH_EARLY_Z, -1.0, -1.0, true}, BUG_BROKEN_DISCARD_WITH_EARLY_Z, -1.0, -1.0, true},
{API_VULKAN, OS_OSX, VENDOR_INTEL, DRIVER_PORTABILITY, Family::UNKNOWN,
BUG_BROKEN_DYNAMIC_SAMPLER_INDEXING, -1.0, -1.0, true},
}; };
static std::map<Bug, BugInfo> m_bugs; static std::map<Bug, BugInfo> m_bugs;

6
Source/Core/VideoCommon/DriverDetails.h
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@ -320,6 +320,12 @@ enum Bug
// Started version: -1 // Started version: -1
// Ended version: -1 // Ended version: -1
BUG_BROKEN_DISCARD_WITH_EARLY_Z, BUG_BROKEN_DISCARD_WITH_EARLY_Z,
// BUG: Using dynamic sampler indexing locks up the GPU
// Affected devices: Intel (macOS Metal)
// Started version: -1
// Ended version: -1
BUG_BROKEN_DYNAMIC_SAMPLER_INDEXING,
}; };
// Initializes our internal vendor, device family, and driver version // Initializes our internal vendor, device family, and driver version

23
Source/Core/VideoCommon/UberShaderPixel.cpp
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@ -485,14 +485,6 @@ ShaderCode GenPixelShader(APIType api_type, const ShaderHostConfig& host_config,
"\n" "\n"
"int4 getTevReg(in State s, uint index) {{\n"); "int4 getTevReg(in State s, uint index) {{\n");
WriteSwitch(out, api_type, "index", tev_regs_lookup_table, 2, false); WriteSwitch(out, api_type, "index", tev_regs_lookup_table, 2, false);
out.Write("}}\n"
"\n"
"void setRegColor(inout State s, uint index, int3 color) {{\n");
WriteSwitch(out, api_type, "index", tev_c_set_table, 2, true);
out.Write("}}\n"
"\n"
"void setRegAlpha(inout State s, uint index, int alpha) {{\n");
WriteSwitch(out, api_type, "index", tev_a_set_table, 2, true);
out.Write("}}\n" out.Write("}}\n"
"\n"); "\n");
@ -798,9 +790,9 @@ ShaderCode GenPixelShader(APIType api_type, const ShaderHostConfig& host_config,
" else\n" " else\n"
" color = clamp(color, -1024, 1023);\n" " color = clamp(color, -1024, 1023);\n"
"\n" "\n"
" // Write result to the correct input register of the next stage\n" " // Write result to the correct input register of the next stage\n");
" setRegColor(s, color_dest, color);\n" WriteSwitch(out, api_type, "color_dest", tev_c_set_table, 6, true);
"\n"); out.Write("\n");
// Alpha combiner // Alpha combiner
out.Write(" // Alpha Combiner\n"); out.Write(" // Alpha Combiner\n");
@ -864,11 +856,10 @@ ShaderCode GenPixelShader(APIType api_type, const ShaderHostConfig& host_config,
" else\n" " else\n"
" alpha = clamp(alpha, -1024, 1023);\n" " alpha = clamp(alpha, -1024, 1023);\n"
"\n" "\n"
" // Write result to the correct input register of the next stage\n" " // Write result to the correct input register of the next stage\n");
" setRegAlpha(s, alpha_dest, alpha);\n" WriteSwitch(out, api_type, "alpha_dest", tev_a_set_table, 6, true);
" }}\n"); out.Write(" }}\n"
" }} // Main TEV loop\n"
out.Write(" }} // Main TEV loop\n"
"\n"); "\n");
// Select the output color and alpha registers from the last stage. // Select the output color and alpha registers from the last stage.