From cd027f4091f2e692994937d0bd86388bafd3b4f6 Mon Sep 17 00:00:00 2001
From: JosJuice <josjuice@gmail.com>
Date: Tue, 18 Oct 2022 22:18:53 +0200
Subject: [PATCH] JitArm64: Cram two constants into one register

---
 Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp | 4 ++--
 .../Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp  | 2 +-
 Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp      | 1 +
 Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h        | 5 ++---
 Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp                 | 5 ++---
 5 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
index 8712fdd2a2..8e167dc7d8 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
@@ -575,8 +575,8 @@ void JitArm64::fctiwx(UGeckoInstruction inst)
       m_float_emit.FCVTS(EncodeRegToSingle(VD), EncodeRegToSingle(VD), RoundingMode::Z);
     }
 
-    m_float_emit.ORR(EncodeRegToDouble(VD), EncodeRegToDouble(VD),
-                     EncodeRegToDouble(FPR_CONSTANT_FFF8_0000_0000_0000));
+    m_float_emit.INS(32, EncodeRegToDouble(VD), 1,
+                     EncodeRegToDouble(FPR_CONSTANT_FFF8_0000_3F80_0000), 1);
   }
   else
   {
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
index 4fee7f3454..3d5f4ac8c5 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
@@ -121,7 +121,7 @@ void JitArm64::psq_lXX(UGeckoInstruction inst)
   if (w)
   {
     // Set ps1 to 1.0
-    m_float_emit.INS(32, VS, 1, FPR_CONSTANT_0000_0000_3F80_0000, 0);
+    m_float_emit.INS(32, VS, 1, FPR_CONSTANT_FFF8_0000_3F80_0000, 0);
   }
 
   const ARM64Reg VS_again = fpr.RW(inst.RS, RegType::Single, true);
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp
index 236f95dbed..8c038fce25 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp
@@ -726,6 +726,7 @@ void Arm64FPRCache::GetAllocationOrder()
       ARM64Reg::Q10,
       ARM64Reg::Q11,
       ARM64Reg::Q12,
+      ARM64Reg::Q13,
 
       // Caller saved
       ARM64Reg::Q16,
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h b/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h
index 3534d335a7..805a0f8266 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h
@@ -26,9 +26,8 @@ constexpr Arm64Gen::ARM64Reg PPC_REG = Arm64Gen::ARM64Reg::X29;
 constexpr Arm64Gen::ARM64Reg DISPATCHER_PC = Arm64Gen::ARM64Reg::W26;
 
 // FPR constants
-constexpr Arm64Gen::ARM64Reg FPR_CONSTANT_0000_0000_0000_0000 = Arm64Gen::ARM64Reg::Q13;
-constexpr Arm64Gen::ARM64Reg FPR_CONSTANT_0000_0000_3F80_0000 = Arm64Gen::ARM64Reg::Q14;
-constexpr Arm64Gen::ARM64Reg FPR_CONSTANT_FFF8_0000_0000_0000 = Arm64Gen::ARM64Reg::Q15;
+constexpr Arm64Gen::ARM64Reg FPR_CONSTANT_0000_0000_0000_0000 = Arm64Gen::ARM64Reg::Q14;
+constexpr Arm64Gen::ARM64Reg FPR_CONSTANT_FFF8_0000_3F80_0000 = Arm64Gen::ARM64Reg::Q15;
 
 #ifdef __GNUC__
 #define PPCSTATE_OFF(elem)                                                                         \
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
index 063c10b380..b948e17cea 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
@@ -46,9 +46,8 @@ void JitArm64::GenerateAsm()
 
   // Generate FPR constants
   m_float_emit.MOVI(8, EncodeRegToDouble(FPR_CONSTANT_0000_0000_0000_0000), 0);
-  m_float_emit.FMOV(EncodeRegToSingle(FPR_CONSTANT_0000_0000_3F80_0000), 0x70);
-  MOVI2R(ARM64Reg::X30, 0xFFF8'0000'0000'0000ULL);
-  m_float_emit.FMOV(EncodeRegToDouble(FPR_CONSTANT_FFF8_0000_0000_0000), ARM64Reg::X30);
+  MOVI2R(ARM64Reg::X30, 0xFFF8'0000'3F80'0000ULL);
+  m_float_emit.FMOV(EncodeRegToDouble(FPR_CONSTANT_FFF8_0000_3F80_0000), ARM64Reg::X30);
 
   MOVP2R(PPC_REG, &m_ppc_state);