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Disable JitArm64's inline timebase implemenation, as it's incorrect.

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The interpeted version is correct.
This commit is contained in:
Scott Mansell 2016-03-24 05:11:54 +13:00
parent 27beef1ff4
commit d61baef2f6
1 changed files with 8 additions and 4 deletions
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12
Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp
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@ -224,6 +224,10 @@ void JitArm64::mfspr(UGeckoInstruction inst)
case SPR_TL: case SPR_TL:
case SPR_TU: case SPR_TU:
{ {
// The inline implementation here is inaccurate and out of date as of PR3601
FALLBACK_IF(true); // Fallback to interpreted version.
/*
ARM64Reg WA = gpr.GetReg(); ARM64Reg WA = gpr.GetReg();
ARM64Reg WB = gpr.GetReg(); ARM64Reg WB = gpr.GetReg();
ARM64Reg XA = EncodeRegTo64(WA); ARM64Reg XA = EncodeRegTo64(WA);
@ -231,9 +235,9 @@ void JitArm64::mfspr(UGeckoInstruction inst)
// An inline implementation of CoreTiming::GetFakeTimeBase, since in timer-heavy games the // An inline implementation of CoreTiming::GetFakeTimeBase, since in timer-heavy games the
// cost of calling out to C for this is actually significant. // cost of calling out to C for this is actually significant.
MOVI2R(XA, (u64)&CoreTiming::globalTimer); MOVI2R(XA, (u64)&CoreTiming::g_globalTimer);
LDR(INDEX_UNSIGNED, XA, XA, 0); LDR(INDEX_UNSIGNED, XA, XA, 0);
MOVI2R(XB, (u64)&CoreTiming::fakeTBStartTicks); MOVI2R(XB, (u64)&CoreTiming::g_fakeTBStartTicks);
LDR(INDEX_UNSIGNED, XB, XB, 0); LDR(INDEX_UNSIGNED, XB, XB, 0);
SUB(XA, XA, XB); SUB(XA, XA, XB);
@ -247,7 +251,7 @@ void JitArm64::mfspr(UGeckoInstruction inst)
ADD(XB, XB, 1); ADD(XB, XB, 1);
UMULH(XA, XA, XB); UMULH(XA, XA, XB);
MOVI2R(XB, (u64)&CoreTiming::fakeTBStartValue); MOVI2R(XB, (u64)&CoreTiming::g_fakeTBStartValue);
LDR(INDEX_UNSIGNED, XB, XB, 0); LDR(INDEX_UNSIGNED, XB, XB, 0);
ADD(XA, XB, XA, ArithOption(XA, ST_LSR, 3)); ADD(XA, XB, XA, ArithOption(XA, ST_LSR, 3));
STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(spr[SPR_TL])); STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(spr[SPR_TL]));
@ -285,7 +289,7 @@ void JitArm64::mfspr(UGeckoInstruction inst)
ORR(EncodeRegTo64(gpr.R(d)), SP, XA, ArithOption(XA, ST_LSR, 32)); ORR(EncodeRegTo64(gpr.R(d)), SP, XA, ArithOption(XA, ST_LSR, 32));
else else
MOV(gpr.R(d), WA); MOV(gpr.R(d), WA);
gpr.Unlock(WA, WB); gpr.Unlock(WA, WB);*/
} }
break; break;
case SPR_XER: case SPR_XER: