From d87ec716158ac270cd1847d40ab0c28866562638 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Wed, 30 Dec 2020 20:20:47 -0500
Subject: [PATCH] Arm64Emitter: Make PStateField enum an enum class

Prevents namespace pollution and makes the enum members strongly typed.
---
 Source/Core/Common/Arm64Emitter.cpp | 16 ++++++++--------
 Source/Core/Common/Arm64Emitter.h   | 18 +++++++++---------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/Source/Core/Common/Arm64Emitter.cpp b/Source/Core/Common/Arm64Emitter.cpp
index b8e808513c..6246ae7b71 100644
--- a/Source/Core/Common/Arm64Emitter.cpp
+++ b/Source/Core/Common/Arm64Emitter.cpp
@@ -1149,15 +1149,15 @@ void ARM64XEmitter::_MSR(PStateField field, u8 imm)
   u32 op1 = 0, op2 = 0;
   switch (field)
   {
-  case FIELD_SPSel:
+  case PStateField::SPSel:
     op1 = 0;
     op2 = 5;
     break;
-  case FIELD_DAIFSet:
+  case PStateField::DAIFSet:
     op1 = 3;
     op2 = 6;
     break;
-  case FIELD_DAIFClr:
+  case PStateField::DAIFClr:
     op1 = 3;
     op2 = 7;
     break;
@@ -1172,35 +1172,35 @@ static void GetSystemReg(PStateField field, int& o0, int& op1, int& CRn, int& CR
 {
   switch (field)
   {
-  case FIELD_NZCV:
+  case PStateField::NZCV:
     o0 = 3;
     op1 = 3;
     CRn = 4;
     CRm = 2;
     op2 = 0;
     break;
-  case FIELD_FPCR:
+  case PStateField::FPCR:
     o0 = 3;
     op1 = 3;
     CRn = 4;
     CRm = 4;
     op2 = 0;
     break;
-  case FIELD_FPSR:
+  case PStateField::FPSR:
     o0 = 3;
     op1 = 3;
     CRn = 4;
     CRm = 4;
     op2 = 1;
     break;
-  case FIELD_PMCR_EL0:
+  case PStateField::PMCR_EL0:
     o0 = 3;
     op1 = 3;
     CRn = 9;
     CRm = 6;
     op2 = 0;
     break;
-  case FIELD_PMCCNTR_EL0:
+  case PStateField::PMCCNTR_EL0:
     o0 = 3;
     op1 = 3;
     CRn = 9;
diff --git a/Source/Core/Common/Arm64Emitter.h b/Source/Core/Common/Arm64Emitter.h
index b631de0760..5fae0dd3d0 100644
--- a/Source/Core/Common/Arm64Emitter.h
+++ b/Source/Core/Common/Arm64Emitter.h
@@ -342,16 +342,16 @@ struct FixupBranch
   ARM64Reg reg;
 };
 
-enum PStateField
+enum class PStateField
 {
-  FIELD_SPSel = 0,
-  FIELD_DAIFSet,
-  FIELD_DAIFClr,
-  FIELD_NZCV,  // The only system registers accessible from EL0 (user space)
-  FIELD_PMCR_EL0,
-  FIELD_PMCCNTR_EL0,
-  FIELD_FPCR = 0x340,
-  FIELD_FPSR = 0x341,
+  SPSel = 0,
+  DAIFSet,
+  DAIFClr,
+  NZCV,  // The only system registers accessible from EL0 (user space)
+  PMCR_EL0,
+  PMCCNTR_EL0,
+  FPCR = 0x340,
+  FPSR = 0x341,
 };
 
 enum class SystemHint