From dc6e5e7ff6b78b157b030994520ad20b7e402332 Mon Sep 17 00:00:00 2001 From: JosJuice Date: Sun, 26 May 2024 08:47:20 +0200 Subject: [PATCH] JitArm64: Replace a comparison to SP Comparing with an immediate 0 has the same effect but is much easier to read. --- Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp index 58bb7c6c24..e34be195c4 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp @@ -32,7 +32,7 @@ FixupBranch JitArm64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set) case PowerPC::CR_EQ_BIT: // check bits 31-0 == 0 return jump_if_set ? CBZ(WA) : CBNZ(WA); case PowerPC::CR_GT_BIT: // check val > 0 - CMP(XA, ARM64Reg::SP); + CMP(XA, 0); return B(jump_if_set ? CC_GT : CC_LE); case PowerPC::CR_LT_BIT: // check bit 62 set return jump_if_set ? TBNZ(XA, PowerPC::CR_EMU_LT_BIT) : TBZ(XA, PowerPC::CR_EMU_LT_BIT);