diff --git a/Source/Core/Core/Src/PowerPC/Interpreter/Interpreter_LoadStore.cpp b/Source/Core/Core/Src/PowerPC/Interpreter/Interpreter_LoadStore.cpp index c83b796bca..6687b5a7b2 100644 --- a/Source/Core/Core/Src/PowerPC/Interpreter/Interpreter_LoadStore.cpp +++ b/Source/Core/Core/Src/PowerPC/Interpreter/Interpreter_LoadStore.cpp @@ -579,30 +579,43 @@ void stwbrx(UGeckoInstruction _inst) } -// The following two instructions are for inter-cpu communications. On a single CPU, they cannot -// fail unless an interrupt happens in between, which usually won't happen with the JIT, so we just pretend -// they are regular loads and stores for now. If this proves to be a problem, we could add a reservation flag. +// The following two instructions are for inter-cpu communications. On a single +// CPU, they cannot +// fail unless an interrupt happens in between, which usually won't happen with +// the JIT. +bool g_bReserve = false; +u32 g_reserveAddr; + void lwarx(UGeckoInstruction _inst) { - m_GPR[_inst.RD] = Memory::Read_U32(Helper_Get_EA_X(_inst)); - //static bool bFirst = true; - //if (bFirst) - // MessageBox(NULL, "lwarx", "Instruction unimplemented", MB_OK); - //bFirst = false; + u32 uAddress = Helper_Get_EA_X(_inst); + + m_GPR[_inst.RD] = Memory::Read_U32(uAddress); + g_bReserve = true; + g_reserveAddr = uAddress; } void stwcxd(UGeckoInstruction _inst) { // This instruction, too - static bool bFirst = true; - if (bFirst) - PanicAlert("stwcxd - suspicious instruction"); + //PanicAlert("stwcxd - suspicious instruction"); + + // Stores Word Conditional indeXed + + u32 uAddress; - // TODO: Stores Word Conditional indeXed - - bFirst = false; - u32 uAddress = Helper_Get_EA_X(_inst); - Memory::Write_U32(m_GPR[_inst.RS], uAddress); + if(g_bReserve) { + uAddress = Helper_Get_EA_X(_inst); + if(uAddress == g_reserveAddr) { + Memory::Write_U32(m_GPR[_inst.RS], uAddress); + g_bReserve = false; + + return; + } + + } + + // TODO: Set CR0 to IS_XER_SO } void stwux(UGeckoInstruction _inst)