JitArm64_Integer: Refactor subfex

This commit is contained in:
Sintendo 2024-12-28 18:12:13 +01:00
parent 5cc9bde1c1
commit e54bfd6605

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@ -1216,40 +1216,44 @@ void JitArm64::subfex(UGeckoInstruction inst)
if (gpr.IsImm(a) && (mex || gpr.IsImm(b))) if (gpr.IsImm(a) && (mex || gpr.IsImm(b)))
{ {
u32 i = gpr.GetImm(a), j = mex ? -1 : gpr.GetImm(b); const u32 i = gpr.GetImm(a);
const u32 j = mex ? -1 : gpr.GetImm(b);
gpr.BindToRegister(d, false); const u32 imm = ~i + j;
const bool is_all_ones = imm == 0xFFFFFFFF;
switch (js.carryFlag) switch (js.carryFlag)
{ {
case CarryFlag::InPPCState: case CarryFlag::InPPCState:
{ {
gpr.BindToRegister(d, false);
ARM64Reg RD = gpr.R(d);
auto WA = gpr.GetScopedReg(); auto WA = gpr.GetScopedReg();
LDRB(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(xer_ca)); LDRB(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(xer_ca));
ADDI2R(gpr.R(d), WA, ~i + j, gpr.R(d)); ADDI2R(RD, WA, imm, RD);
break; break;
} }
case CarryFlag::InHostCarry: case CarryFlag::InHostCarry:
{ {
auto WA = gpr.GetScopedReg(); gpr.BindToRegister(d, false);
MOVI2R(WA, ~i + j); ARM64Reg RD = gpr.R(d);
ADC(gpr.R(d), WA, ARM64Reg::WZR); MOVI2R(RD, imm);
ADC(RD, RD, ARM64Reg::WZR);
break; break;
} }
case CarryFlag::ConstantTrue: case CarryFlag::ConstantTrue:
{ {
gpr.SetImmediate(d, ~i + j + 1); gpr.SetImmediate(d, imm + 1);
break; break;
} }
case CarryFlag::ConstantFalse: case CarryFlag::ConstantFalse:
{ {
gpr.SetImmediate(d, ~i + j); gpr.SetImmediate(d, imm);
break; break;
} }
} }
const bool must_have_carry = Interpreter::Helper_Carry(~i, j); const bool must_have_carry = Interpreter::Helper_Carry(~i, j);
const bool might_have_carry = (~i + j) == 0xFFFFFFFF; const bool might_have_carry = is_all_ones;
if (must_have_carry) if (must_have_carry)
{ {