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[ARM] Optimize that fastmem load/stores minimally.

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This commit is contained in:
Ryan Houdek 2013-09-08 07:37:03 +00:00
parent 2126f405e0
commit e5b5713d70
2 changed files with 18 additions and 18 deletions
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5
Source/Core/Core/Src/PowerPC/JitArm32/JitArm_BackPatch.cpp
View File

@ -96,7 +96,7 @@ const u8 *JitArm::BackPatch(u8 *codePtr, u32, void *ctx_void)
if (Store) if (Store)
{ {
const u32 ARMREGOFFSET = 4 * 7; const u32 ARMREGOFFSET = 4 * 5;
ARMXEmitter emitter(codePtr - ARMREGOFFSET); ARMXEmitter emitter(codePtr - ARMREGOFFSET);
switch (accessSize) switch (accessSize)
{ {
@ -117,7 +117,6 @@ const u8 *JitArm::BackPatch(u8 *codePtr, u32, void *ctx_void)
emitter.MOV(R1, R10); // Addr- 5 emitter.MOV(R1, R10); // Addr- 5
emitter.BL(R14); // 6 emitter.BL(R14); // 6
emitter.POP(4, R0, R1, R2, R3); // 7 emitter.POP(4, R0, R1, R2, R3); // 7
emitter.NOP(1); // 8
u32 newPC = ctx->reg_pc - (ARMREGOFFSET + 4 * 4); u32 newPC = ctx->reg_pc - (ARMREGOFFSET + 4 * 4);
ctx->reg_pc = newPC; ctx->reg_pc = newPC;
emitter.FlushIcache(); emitter.FlushIcache();
@ -125,7 +124,7 @@ const u8 *JitArm::BackPatch(u8 *codePtr, u32, void *ctx_void)
} }
else else
{ {
const u32 ARMREGOFFSET = 4 * 6; const u32 ARMREGOFFSET = 4 * 4;
ARMXEmitter emitter(codePtr - ARMREGOFFSET); ARMXEmitter emitter(codePtr - ARMREGOFFSET);
switch (accessSize) switch (accessSize)
{ {

31
Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp
View File

@ -33,16 +33,15 @@
void JitArm::UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset) void JitArm::UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset)
{ {
// All this gets replaced on backpatch // All this gets replaced on backpatch
MOVI2R(R14, Memory::MEMVIEW32_MASK, false); // 1-2 Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
AND(dest, dest, R14); // 3 BIC(dest, dest, mask); // 1
MOVI2R(R14, (u32)Memory::base, false); // 4-5 MOVI2R(R14, (u32)Memory::base, false); // 2-3
ADD(dest, dest, R14); // 6 ADD(dest, dest, R14); // 4
switch (accessSize) switch (accessSize)
{ {
case 32: case 32:
REV(value, value); // 7 REV(value, value); // 5
break; break;
case 16: case 16:
REV16(value, value); REV16(value, value);
@ -54,7 +53,7 @@ void JitArm::UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 o
switch (accessSize) switch (accessSize)
{ {
case 32: case 32:
STR(value, dest); // 8 STR(value, dest); // 6
break; break;
case 16: case 16:
STRH(value, dest); STRH(value, dest);
@ -63,6 +62,7 @@ void JitArm::UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 o
STRB(value, dest); STRB(value, dest);
break; break;
} }
NOP(1); // 7
} }
void JitArm::SafeStoreFromReg(bool fastmem, s32 dest, u32 value, s32 regOffset, int accessSize, s32 offset) void JitArm::SafeStoreFromReg(bool fastmem, s32 dest, u32 value, s32 regOffset, int accessSize, s32 offset)
@ -224,14 +224,14 @@ void JitArm::UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offse
ADD(addr, addr, rA); // - 1 ADD(addr, addr, rA); // - 1
// All this gets replaced on backpatch // All this gets replaced on backpatch
MOVI2R(rA, Memory::MEMVIEW32_MASK, false); // 2 Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
AND(addr, addr, rA); // 3 BIC(addr, addr, mask); // 1
MOVI2R(rA, (u32)Memory::base, false); // 5 MOVI2R(rA, (u32)Memory::base, false); // 2-3
ADD(addr, addr, rA); // 6 ADD(addr, addr, rA); // 4
switch (accessSize) switch (accessSize)
{ {
case 32: case 32:
LDR(dest, addr); // 7 LDR(dest, addr); // 5
break; break;
case 16: case 16:
LDRH(dest, addr); LDRH(dest, addr);
@ -243,7 +243,7 @@ void JitArm::UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offse
switch (accessSize) switch (accessSize)
{ {
case 32: case 32:
REV(dest, dest); // 9 REV(dest, dest); // 6
break; break;
case 16: case 16:
REV16(dest, dest); REV16(dest, dest);
@ -253,6 +253,7 @@ void JitArm::UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offse
break; break;
} }
NOP(2); // 7-8
gpr.Unlock(rA); gpr.Unlock(rA);
} }
@ -460,8 +461,8 @@ void JitArm::lmw(UGeckoInstruction inst)
MOVI2R(rA, inst.SIMM_16); MOVI2R(rA, inst.SIMM_16);
if (a) if (a)
ADD(rA, rA, gpr.R(a)); ADD(rA, rA, gpr.R(a));
MOVI2R(rB, Memory::MEMVIEW32_MASK, false); // 1-2 Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
AND(rA, rA, rB); // 3 BIC(rA, rA, mask); // 3
MOVI2R(rB, (u32)Memory::base, false); // 4-5 MOVI2R(rB, (u32)Memory::base, false); // 4-5
ADD(rA, rA, rB); // 6 ADD(rA, rA, rB); // 6