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small cleanup in dsp lle

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I wonder if we should bother making DMAs take time?

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5217 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Shawn Hoffman 2010-03-20 20:56:33 +00:00
parent 503bf545a3
commit e94229cba0
1 changed files with 32 additions and 23 deletions
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55
Source/Core/DSPCore/Src/DSPHWInterface.cpp
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@ -129,34 +129,39 @@ void gdsp_ifx_write(u16 addr, u16 val)
{ {
switch (addr & 0xff) switch (addr & 0xff)
{ {
case 0xfb: // DIRQ case DSP_DIRQ:
if (val & 0x1) if (val & 0x1)
DSPHost_InterruptRequest(); DSPHost_InterruptRequest();
else else
INFO_LOG(DSPLLE, "Unknown Interrupt Request pc=%04x (%04x)", g_dsp.pc, val); INFO_LOG(DSPLLE, "Unknown Interrupt Request pc=%04x (%04x)", g_dsp.pc, val);
break; break;
case 0xfc: // DMBH case DSP_DMBH:
gdsp_mbox_write_h(GDSP_MBOX_DSP, val); gdsp_mbox_write_h(GDSP_MBOX_DSP, val);
break; break;
case 0xfd: // DMBL case DSP_DMBL:
gdsp_mbox_write_l(GDSP_MBOX_DSP, val); gdsp_mbox_write_l(GDSP_MBOX_DSP, val);
break; break;
case 0xfe: // CMBH case DSP_CMBH:
return gdsp_mbox_write_h(GDSP_MBOX_CPU, val); return gdsp_mbox_write_h(GDSP_MBOX_CPU, val);
case 0xff: // CMBL case DSP_CMBL:
return gdsp_mbox_write_l(GDSP_MBOX_CPU, val); return gdsp_mbox_write_l(GDSP_MBOX_CPU, val);
case 0xcb: // DSBL case DSP_DSBL:
g_dsp.ifx_regs[addr & 0xFF] = val; g_dsp.ifx_regs[DSP_DSBL] = val;
gdsp_do_dma(); g_dsp.ifx_regs[DSP_DSCR] |= 4; // Doesn't really matter since we do DMA instantly
g_dsp.ifx_regs[DSP_DSCR] &= ~0x0004; if (!g_dsp.ifx_regs[DSP_AMDM])
gdsp_do_dma();
else
NOTICE_LOG(DSPLLE, "Masked DMA skipped");
g_dsp.ifx_regs[DSP_DSCR] &= ~4;
g_dsp.ifx_regs[DSP_DSBL] = 0;
break; break;
case 0xd3: // Accelerator write (Zelda type) - "UnkZelda" case DSP_ACDATA1: // Accelerator write (Zelda type) - "UnkZelda"
dsp_write_aram_d3(val); dsp_write_aram_d3(val);
break; break;
@ -164,13 +169,17 @@ void gdsp_ifx_write(u16 addr, u16 val)
if (val) { if (val) {
INFO_LOG(DSPLLE,"Gain Written: 0x%04x", val); INFO_LOG(DSPLLE,"Gain Written: 0x%04x", val);
} }
case 0xcd: case DSP_DSPA:
case 0xce: case DSP_DSMAH:
case 0xcf: case DSP_DSMAL:
case 0xc9: case DSP_DSCR:
g_dsp.ifx_regs[addr & 0xFF] = val; g_dsp.ifx_regs[addr & 0xFF] = val;
break; break;
/*
case DSP_ACCAL:
dsp_step_accelerator();
break;
*/
default: default:
if ((addr & 0xff) >= 0xa0) { if ((addr & 0xff) >= 0xa0) {
if (pdlabels[(addr & 0xFF) - 0xa0].name && pdlabels[(addr & 0xFF) - 0xa0].description) { if (pdlabels[(addr & 0xFF) - 0xa0].name && pdlabels[(addr & 0xFF) - 0xa0].description) {
@ -192,25 +201,25 @@ u16 gdsp_ifx_read(u16 addr)
{ {
switch (addr & 0xff) switch (addr & 0xff)
{ {
case 0xfc: // DMBH case DSP_DMBH:
return gdsp_mbox_read_h(GDSP_MBOX_DSP); return gdsp_mbox_read_h(GDSP_MBOX_DSP);
case 0xfd: // DMBL case DSP_DMBL:
return gdsp_mbox_read_l(GDSP_MBOX_DSP); return gdsp_mbox_read_l(GDSP_MBOX_DSP);
case 0xfe: // CMBH case DSP_CMBH:
return gdsp_mbox_read_h(GDSP_MBOX_CPU); return gdsp_mbox_read_h(GDSP_MBOX_CPU);
case 0xff: // CMBL case DSP_CMBL:
return gdsp_mbox_read_l(GDSP_MBOX_CPU); return gdsp_mbox_read_l(GDSP_MBOX_CPU);
case 0xc9: case DSP_DSCR:
return g_dsp.ifx_regs[addr & 0xFF]; return g_dsp.ifx_regs[addr & 0xFF];
case 0xdd: // ADPCM Accelerator reads case DSP_ACCELERATOR: // ADPCM Accelerator reads
return dsp_read_accelerator(); return dsp_read_accelerator();
case 0xd3: // Accelerator reads (Zelda type) - "UnkZelda" case DSP_ACDATA1: // Accelerator reads (Zelda type) - "UnkZelda"
return dsp_read_aram_d3(); return dsp_read_aram_d3();
default: default: