mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-01-10 08:09:26 +01:00
Misc accumulated Jit64IL work; I don't recall whether any of these
changes individually led to perf improvements, although overall it's spending a lot less time in interpreter fallbacks. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@1904 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
magumagu9
parent
9cb25d6ba2
commit
ee2bf31e56
@ -38,7 +38,7 @@
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//////////////////////////////////////////////////////////////////////////////////////////
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// Include
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// ¯¯¯¯¯¯¯¯¯¯
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#ifdef JITTEST
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#if JITTEST
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#include "../Jit64IL/Jit.h"
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#else
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@ -1197,11 +1197,9 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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case RFIExit:
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case InterpreterBranch:
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case IdleLoop:
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// No liveness effects
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break;
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case ShortIdleLoop:
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case Tramp:
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if (thisUsed)
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regMarkUse(RI, I, I - 1 - (*I >> 8), 1);
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// No liveness effects
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break;
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case SExt8:
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case SExt16:
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@ -1232,6 +1230,7 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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break;
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case StoreCR:
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case StoreCarry:
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case StoreFPRF:
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regMarkUse(RI, I, getOp1(I), 1);
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break;
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case StoreGReg:
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@ -1277,6 +1276,7 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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case FPMerge01:
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case FPMerge10:
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case FPMerge11:
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case FDCmpCR:
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case InsertDoubleInMReg:
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if (thisUsed) {
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regMarkUse(RI, I, getOp1(I), 1);
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@ -1411,6 +1411,15 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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regNormalRegClear(RI, I);
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break;
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}
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case StoreFPRF: {
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Jit->MOV(32, R(ECX), regLocForInst(RI, getOp1(I)));
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Jit->AND(32, R(ECX), Imm8(0x1F));
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Jit->SHL(32, R(ECX), Imm8(12));
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Jit->AND(32, M(&FPSCR), Imm32(~(0x1F << 12)));
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Jit->OR(32, M(&FPSCR), R(ECX));
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regNormalRegClear(RI, I);
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break;
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}
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case Load8: {
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regEmitMemLoad(RI, I, 8);
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break;
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@ -1851,6 +1860,35 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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fregEmitBinInst(RI, I, &Jit64::SUBSD);
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break;
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}
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case FDCmpCR: {
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X64Reg destreg = regFindFreeReg(RI);
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// TODO: Add case for NaN (CC_P)
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Jit->MOVSD(XMM0, fregLocForInst(RI, getOp1(I)));
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Jit->UCOMISD(XMM0, fregLocForInst(RI, getOp2(I)));
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FixupBranch pNan = Jit->J_CC(CC_P);
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FixupBranch pEqual = Jit->J_CC(CC_Z);
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FixupBranch pLesser = Jit->J_CC(CC_C);
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// Greater
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Jit->MOV(32, R(destreg), Imm32(0x4));
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FixupBranch continue1 = Jit->J();
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// NaN
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Jit->SetJumpTarget(pNan);
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Jit->MOV(32, R(destreg), Imm32(0x1));
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FixupBranch continue2 = Jit->J();
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// Equal
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Jit->SetJumpTarget(pEqual);
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Jit->MOV(32, R(destreg), Imm32(0x2));
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FixupBranch continue3 = Jit->J();
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// Less
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Jit->SetJumpTarget(pLesser);
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Jit->MOV(32, R(destreg), Imm32(0x8));
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Jit->SetJumpTarget(continue1);
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Jit->SetJumpTarget(continue2);
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Jit->SetJumpTarget(continue3);
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RI.regs[destreg] = I;
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fregNormalRegClear(RI, I);
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break;
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}
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case FPAdd: {
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if (!thisUsed) break;
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fregEmitBinInst(RI, I, &Jit64::ADDPS);
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@ -1962,7 +2000,14 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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unsigned IdleParam = ibuild->GetImmValue(getOp1(I));
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unsigned InstLoc = ibuild->GetImmValue(getOp2(I));
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Jit->ABI_CallFunctionC((void *)&PowerPC::OnIdle, IdleParam);
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Jit->MOV(32, M(&PowerPC::ppcState.pc), Imm32(InstLoc + 12));
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Jit->MOV(32, M(&PC), Imm32(InstLoc + 12));
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Jit->JMP(asm_routines.testExceptions, true);
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break;
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}
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case ShortIdleLoop: {
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unsigned InstLoc = ibuild->GetImmValue(getOp1(I));
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Jit->ABI_CallFunction((void *)&CoreTiming::Idle);
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Jit->MOV(32, M(&PC), Imm32(InstLoc));
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Jit->JMP(asm_routines.testExceptions, true);
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break;
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}
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@ -1998,25 +2043,7 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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Jit->WriteRfiExitDestInEAX();
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break;
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}
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case Tramp: {
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if (!thisUsed) break;
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// FIXME: Optimize!
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InstLoc Op = I - 1 - (*I >> 8);
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if (isFResult(*Op)) {
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, Op));
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RI.fregs[reg] = I;
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if (RI.IInfo[I - RI.FirstI] & 4)
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fregClearInst(RI, Op);
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} else {
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X64Reg reg = regFindFreeReg(RI);
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Jit->MOV(32, R(reg), regLocForInst(RI, Op));
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RI.regs[reg] = I;
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if (RI.IInfo[I - RI.FirstI] & 4)
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regClearInst(RI, Op);
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}
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break;
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}
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case Tramp: break;
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case Nop: break;
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default:
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PanicAlert("Unknown JIT instruction; aborting!");
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@ -2034,7 +2061,7 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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}
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}
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if (UseProfile && RI.numSpills)
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if (!RI.MakeProfile && RI.numSpills)
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printf("Block: %x, numspills %d\n", Jit->js.blockStart, RI.numSpills);
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Jit->UD2();
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@ -54,6 +54,7 @@ namespace IREmitter {
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StoreCarry,
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StoreCTR,
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StoreMSR,
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StoreFPRF,
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// Arbitrary interpreter instruction
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InterpreterFallback,
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@ -184,6 +185,7 @@ namespace IREmitter {
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StoreSingle,
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StoreDouble,
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StoreFReg,
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FDCmpCR,
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// "Trinary" operators
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// FIXME: Need to change representation!
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@ -197,7 +199,9 @@ namespace IREmitter {
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SystemCall,
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RFIExit,
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InterpreterBranch,
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IdleLoop,
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IdleLoop, // The "usual" idle loop, load+compare+branch
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ShortIdleLoop, // Idle loop seen in homebrew like wii mahjong,
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// just a branch
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// "Opcode" representing a register too far away to
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// reference directly; this is a size optimization
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@ -227,11 +231,19 @@ namespace IREmitter {
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}
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InstLoc inline getOp1(InstLoc i) {
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return i - 1 - ((*i >> 8) & 255);
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i = i - 1 - ((*i >> 8) & 255);
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if (getOpcode(*i) == Tramp) {
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i = i - 1 - (*i >> 8);
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}
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return i;
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}
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InstLoc inline getOp2(InstLoc i) {
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return i - 1 - ((*i >> 16) & 255);
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i = i - 1 - ((*i >> 16) & 255);
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if (getOpcode(*i) == Tramp) {
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i = i - 1 - (*i >> 8);
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}
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return i;
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}
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class IRBuilder {
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@ -288,6 +300,9 @@ namespace IREmitter {
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InstLoc EmitStoreMSR(InstLoc val) {
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return FoldUOp(StoreMSR, val);
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}
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InstLoc EmitStoreFPRF(InstLoc value) {
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return FoldUOp(StoreFPRF, value);
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}
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InstLoc EmitLoadGReg(unsigned reg) {
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return FoldZeroOp(LoadGReg, reg);
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}
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@ -390,6 +405,9 @@ namespace IREmitter {
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InstLoc EmitInterpreterBranch() {
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return FoldZeroOp(InterpreterBranch, 0);
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}
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InstLoc EmitLoadCarry() {
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return FoldZeroOp(LoadCarry, 0);
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}
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InstLoc EmitStoreCarry(InstLoc op1) {
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return FoldUOp(StoreCarry, op1);
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}
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@ -402,6 +420,9 @@ namespace IREmitter {
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InstLoc EmitIdleLoop(InstLoc idleParam, InstLoc pc) {
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return FoldBiOp(IdleLoop, idleParam, pc);
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}
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InstLoc EmitShortIdleLoop(InstLoc pc) {
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return FoldUOp(ShortIdleLoop, pc);
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}
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InstLoc EmitLoadSingle(InstLoc addr) {
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return FoldUOp(LoadSingle, addr);
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}
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@ -498,6 +519,9 @@ namespace IREmitter {
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InstLoc EmitDoubleToSingle(InstLoc op1) {
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return FoldUOp(DoubleToSingle, op1);
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}
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InstLoc EmitFDCmpCR(InstLoc op1, InstLoc op2) {
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return FoldBiOp(FDCmpCR, op1, op2);
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}
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void StartBackPass() { curReadPtr = &InstList[InstList.size()]; }
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void StartForwardPass() { curReadPtr = &InstList[0]; }
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@ -280,12 +280,9 @@ public:
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void subfx(UGeckoInstruction inst);
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void subfex(UGeckoInstruction inst);
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void lbzx(UGeckoInstruction inst);
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void lwzx(UGeckoInstruction inst);
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void lXzx(UGeckoInstruction inst);
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void lhax(UGeckoInstruction inst);
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void lwzux(UGeckoInstruction inst);
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void stXx(UGeckoInstruction inst);
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void lmw(UGeckoInstruction inst);
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@ -68,6 +68,11 @@ using namespace Gen;
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else
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destination = js.compilerPC + SignExt26(inst.LI << 2);
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if (destination == js.compilerPC) {
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ibuild.EmitShortIdleLoop(ibuild.EmitIntConst(js.compilerPC));
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return;
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}
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ibuild.EmitBranchUncond(ibuild.EmitIntConst(destination));
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}
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@ -109,7 +114,8 @@ using namespace Gen;
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}
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if (!Test) {
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PanicAlert("Unconditional conditional branch?!");
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Test = ibuild.EmitIntConst(1);
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//PanicAlert("Unconditional conditional branch?!");
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}
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u32 destination;
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@ -28,7 +28,7 @@
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void Jit64::fp_arith_s(UGeckoInstruction inst)
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{
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if (inst.Rc || inst.OPCD != 59 || (inst.SUBOP5 != 25 && inst.SUBOP5 != 20 && inst.SUBOP5 != 21)) {
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if (inst.Rc || (inst.SUBOP5 != 25 && inst.SUBOP5 != 20 && inst.SUBOP5 != 21)) {
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Default(inst); return;
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}
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IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA);
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@ -61,22 +61,24 @@
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void Jit64::fmaddXX(UGeckoInstruction inst)
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{
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if (inst.Rc || inst.OPCD != 59) {
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if (inst.Rc) {
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Default(inst); return;
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}
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bool single_precision = inst.OPCD == 59;
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IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA);
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val = ibuild.EmitDoubleToSingle(val);
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val = ibuild.EmitFSMul(val, ibuild.EmitDoubleToSingle(ibuild.EmitLoadFReg(inst.FC)));
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val = ibuild.EmitFDMul(val, ibuild.EmitLoadFReg(inst.FC));
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if (inst.SUBOP5 & 1)
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val = ibuild.EmitFSAdd(val, ibuild.EmitDoubleToSingle(ibuild.EmitLoadFReg(inst.FB)));
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val = ibuild.EmitFDAdd(val, ibuild.EmitLoadFReg(inst.FB));
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else
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val = ibuild.EmitFSSub(val, ibuild.EmitDoubleToSingle(ibuild.EmitLoadFReg(inst.FB)));
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val = ibuild.EmitFDSub(val, ibuild.EmitLoadFReg(inst.FB));
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if (inst.SUBOP5 & 2)
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val = ibuild.EmitFSNeg(val);
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val = ibuild.EmitFDNeg(val);
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if (inst.OPCD == 59) {
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val = ibuild.EmitDoubleToSingle(val);
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val = ibuild.EmitDupSingleToMReg(val);
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} else {
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val = ibuild.EmitInsertDoubleInMReg(val, ibuild.EmitLoadFReg(inst.FD));
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}
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ibuild.EmitStoreFReg(val, inst.FD);
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}
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@ -92,6 +94,11 @@
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void Jit64::fcmpx(UGeckoInstruction inst)
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{
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Default(inst);
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return;
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printf("fcmpx at %x\n", js.compilerPC);
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IREmitter::InstLoc lhs, rhs, res;
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lhs = ibuild.EmitLoadFReg(inst.FA);
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rhs = ibuild.EmitLoadFReg(inst.FB);
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res = ibuild.EmitFDCmpCR(lhs, rhs);
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ibuild.EmitStoreFPRF(res);
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ibuild.EmitStoreCR(res, inst.CRFD);
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}
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@ -211,19 +211,21 @@
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void Jit64::subfex(UGeckoInstruction inst)
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{
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INSTRUCTION_START;
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Default(inst);
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return;
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/*
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u32 a = m_GPR[_inst.RA];
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u32 b = m_GPR[_inst.RB];
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int carry = GetCarry();
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m_GPR[_inst.RD] = (~a) + b + carry;
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SetCarry(Helper_Carry(~a, b) || Helper_Carry((~a) + b, carry));
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if (_inst.OE) PanicAlert("OE: subfcx");
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if (_inst.Rc) Helper_UpdateCR0(m_GPR[_inst.RD]);
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*/
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if (inst.OE) PanicAlert("OE: subfex");
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IREmitter::InstLoc val, test, lhs, rhs, carry;
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rhs = ibuild.EmitLoadGReg(inst.RA);
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carry = ibuild.EmitLoadCarry();
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rhs = ibuild.EmitXor(rhs, ibuild.EmitIntConst(-1));
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rhs = ibuild.EmitAdd(rhs, carry);
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test = ibuild.EmitICmpEq(rhs, ibuild.EmitIntConst(0));
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test = ibuild.EmitAnd(test, carry);
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lhs = ibuild.EmitLoadGReg(inst.RB);
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val = ibuild.EmitAdd(lhs, rhs);
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ibuild.EmitStoreGReg(val, inst.RD);
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test = ibuild.EmitOr(test, ibuild.EmitICmpUgt(lhs, val));
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ibuild.EmitStoreCarry(test);
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if (inst.Rc)
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ComputeRC(ibuild, val);
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}
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void Jit64::subfx(UGeckoInstruction inst)
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@ -39,24 +39,6 @@
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//#define INSTRUCTION_START Default(inst); return;
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#define INSTRUCTION_START
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void Jit64::lbzx(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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IREmitter::InstLoc addr = ibuild.EmitLoadGReg(inst.RB);
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if (inst.RA)
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addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
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ibuild.EmitStoreGReg(ibuild.EmitLoad8(addr), inst.RD);
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}
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void Jit64::lwzx(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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IREmitter::InstLoc addr = ibuild.EmitLoadGReg(inst.RB);
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if (inst.RA)
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addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
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ibuild.EmitStoreGReg(ibuild.EmitLoad32(addr), inst.RD);
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}
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void Jit64::lhax(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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@ -113,15 +95,24 @@ void Jit64::lha(UGeckoInstruction inst)
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ibuild.EmitStoreGReg(val, inst.RD);
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}
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void Jit64::lwzux(UGeckoInstruction inst)
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void Jit64::lXzx(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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IREmitter::InstLoc addr = ibuild.EmitLoadGReg(inst.RB);
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if (inst.RA) {
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addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
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if (inst.SUBOP10 & 32)
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ibuild.EmitStoreGReg(addr, inst.RA);
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}
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ibuild.EmitStoreGReg(ibuild.EmitLoad32(addr), inst.RD);
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IREmitter::InstLoc val;
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switch (inst.SUBOP10 & ~32)
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{
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default: PanicAlert("lXzx: invalid access size");
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case 23: val = ibuild.EmitLoad32(addr); break; //lwzx
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case 279: val = ibuild.EmitLoad16(addr); break; //lhzx
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case 87: val = ibuild.EmitLoad8(addr); break; //lbzx
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}
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ibuild.EmitStoreGReg(val, inst.RD);
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}
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// Zero cache line.
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@ -183,10 +174,28 @@ void Jit64::stXx(UGeckoInstruction inst)
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// A few games use these heavily in video codecs.
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void Jit64::lmw(UGeckoInstruction inst)
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{
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Default(inst); return;
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INSTRUCTION_START
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||||
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16);
|
||||
if (inst.RA)
|
||||
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
|
||||
for (int i = inst.RD; i < 32; i++)
|
||||
{
|
||||
IREmitter::InstLoc val = ibuild.EmitLoad32(addr);
|
||||
ibuild.EmitStoreGReg(val, i);
|
||||
addr = ibuild.EmitAdd(addr, ibuild.EmitIntConst(4));
|
||||
}
|
||||
}
|
||||
|
||||
void Jit64::stmw(UGeckoInstruction inst)
|
||||
{
|
||||
Default(inst); return;
|
||||
INSTRUCTION_START
|
||||
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16);
|
||||
if (inst.RA)
|
||||
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
|
||||
for (int i = inst.RD; i < 32; i++)
|
||||
{
|
||||
IREmitter::InstLoc val = ibuild.EmitLoadGReg(i);
|
||||
ibuild.EmitStore32(val, addr);
|
||||
addr = ibuild.EmitAdd(addr, ibuild.EmitIntConst(4));
|
||||
}
|
||||
}
|
||||
|
||||
@ -167,12 +167,21 @@ static GekkoOPTemplate primarytable[] =
|
||||
{28, Interpreter::andi_rc, &Jit64::reg_imm, {"andi_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
|
||||
{29, Interpreter::andis_rc, &Jit64::reg_imm, {"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
|
||||
|
||||
#if JITTEST
|
||||
{32, Interpreter::lwz, &Jit64::lXz, {"lwz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
|
||||
{33, Interpreter::lwzu, &Jit64::lXz, {"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
|
||||
{34, Interpreter::lbz, &Jit64::lXz, {"lbz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
|
||||
{35, Interpreter::lbzu, &Jit64::lXz, {"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
|
||||
{40, Interpreter::lhz, &Jit64::lXz, {"lhz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
|
||||
{41, Interpreter::lhzu, &Jit64::lXz, {"lhzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
|
||||
#else
|
||||
{32, Interpreter::lwz, &Jit64::lXz, {"lwz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
|
||||
{33, Interpreter::lwzu, &Jit64::Default, {"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
|
||||
{34, Interpreter::lbz, &Jit64::lXz, {"lbz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
|
||||
{35, Interpreter::lbzu, &Jit64::Default, {"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
|
||||
{40, Interpreter::lhz, &Jit64::lXz, {"lhz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
|
||||
{41, Interpreter::lhzu, &Jit64::Default, {"lhzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
|
||||
#endif
|
||||
{42, Interpreter::lha, &Jit64::lha, {"lha", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
|
||||
{43, Interpreter::lhau, &Jit64::Default, {"lhau", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
|
||||
|
||||
@ -302,13 +311,33 @@ static GekkoOPTemplate table31[] =
|
||||
{24, Interpreter::slwx, &Jit64::slwx, {"slwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
|
||||
|
||||
{54, Interpreter::dcbst, &Jit64::Default, {"dcbst", OPTYPE_DCACHE, 0, 4}},
|
||||
#if JITTEST
|
||||
{86, Interpreter::dcbf, &Jit64::DoNothing, {"dcbf", OPTYPE_DCACHE, 0, 4}},
|
||||
#else
|
||||
{86, Interpreter::dcbf, &Jit64::Default, {"dcbf", OPTYPE_DCACHE, 0, 4}},
|
||||
#endif
|
||||
{246, Interpreter::dcbtst, &Jit64::Default, {"dcbtst", OPTYPE_DCACHE, 0, 1}},
|
||||
{278, Interpreter::dcbt, &Jit64::Default, {"dcbt", OPTYPE_DCACHE, 0, 1}},
|
||||
{470, Interpreter::dcbi, &Jit64::Default, {"dcbi", OPTYPE_DCACHE, 0, 4}},
|
||||
{758, Interpreter::dcba, &Jit64::Default, {"dcba", OPTYPE_DCACHE, 0, 4}},
|
||||
{1014, Interpreter::dcbz, &Jit64::dcbz, {"dcbz", OPTYPE_DCACHE, 0, 4}},
|
||||
#if JITTEST
|
||||
//load word
|
||||
{23, Interpreter::lwzx, &Jit64::lXzx, {"lwzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
|
||||
{55, Interpreter::lwzux, &Jit64::lXzx, {"lwzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
|
||||
|
||||
//load halfword
|
||||
{279, Interpreter::lhzx, &Jit64::lXzx, {"lhzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
|
||||
{311, Interpreter::lhzux, &Jit64::lXzx, {"lhzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
|
||||
|
||||
//load halfword signextend
|
||||
{343, Interpreter::lhax, &Jit64::lhax, {"lhax", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
|
||||
{375, Interpreter::lhaux, &Jit64::Default, {"lhaux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
|
||||
|
||||
//load byte
|
||||
{87, Interpreter::lbzx, &Jit64::lXzx, {"lbzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
|
||||
{119, Interpreter::lbzux, &Jit64::lXzx, {"lbzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
|
||||
#else
|
||||
//load word
|
||||
{23, Interpreter::lwzx, &Jit64::lwzx, {"lwzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
|
||||
{55, Interpreter::lwzux, &Jit64::lwzux, {"lwzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
|
||||
@ -324,7 +353,7 @@ static GekkoOPTemplate table31[] =
|
||||
//load byte
|
||||
{87, Interpreter::lbzx, &Jit64::lbzx, {"lbzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
|
||||
{119, Interpreter::lbzux, &Jit64::Default, {"lbzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
|
||||
|
||||
#endif
|
||||
//load byte reverse
|
||||
{534, Interpreter::lwbrx, &Jit64::Default, {"lwbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
|
||||
{790, Interpreter::lhbrx, &Jit64::Default, {"lhbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user