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https://github.com/dolphin-emu/dolphin.git
synced 2025-01-09 15:49:25 +01:00
maybe fix some crashes some people are seeing (used wrong instruction to load 64 bits)
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@174 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -25,15 +25,16 @@ namespace Gen
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static bool mode32 = false;
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static bool mode32 = false;
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static bool enableBranchHints = false;
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static bool enableBranchHints = false;
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void SetCodePtr(u8 *ptr)
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void SetCodePtr(u8 *ptr)
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{
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{
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code = ptr;
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code = ptr;
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}
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}
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const u8 *GetCodePtr()
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const u8 *GetCodePtr()
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{
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{
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return code;
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return code;
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}
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}
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u8 *GetWritableCodePtr()
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u8 *GetWritableCodePtr()
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{
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{
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return code;
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return code;
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@ -107,18 +108,18 @@ namespace Gen
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{
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{
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#ifdef _M_X64
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#ifdef _M_X64
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u8 op = 0x40;
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u8 op = 0x40;
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if (customOp == -1) customOp = operandReg;
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if (customOp == -1) customOp = operandReg;
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if (op64) op |= 8;
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if (op64) op |= 8;
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if (customOp >> 3) op |= 4;
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if (customOp >> 3) op |= 4;
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if (indexReg >> 3) op |= 2;
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if (indexReg >> 3) op |= 2;
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if (offsetOrBaseReg >> 3) op |= 1; //TODO investigate if this is dangerous
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if (offsetOrBaseReg >> 3) op |= 1; //TODO investigate if this is dangerous
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_dbg_assert_msg_(DYNA_REC,!mode32 || op == 0x40,"!mode32");
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_dbg_assert_msg_(DYNA_REC, !mode32 || op == 0x40, "!mode32");
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if (op != 0x40)
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if (op != 0x40)
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Write8(op);
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Write8(op);
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#else
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#else
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_dbg_assert_(DYNA_REC,(operandReg >> 3) == 0);
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_dbg_assert_(DYNA_REC, (operandReg >> 3) == 0);
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_dbg_assert_(DYNA_REC,(indexReg >> 3) == 0);
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_dbg_assert_(DYNA_REC, (indexReg >> 3) == 0);
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_dbg_assert_(DYNA_REC,(offsetOrBaseReg >> 3) == 0);
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_dbg_assert_(DYNA_REC, (offsetOrBaseReg >> 3) == 0);
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#endif
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#endif
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}
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}
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@ -970,6 +971,53 @@ namespace Gen
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arg.WriteRest(extrabytes);
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arg.WriteRest(extrabytes);
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}
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}
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void MOVD_xmm(X64Reg dest, const OpArg &arg) {WriteSSEOp(64, 0x6E, true, dest, arg, 0);}
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void MOVQ_xmm(X64Reg dest, OpArg arg) {
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if (dest > 7)
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{
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// Alternate encoding
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// This does not display correctly in MSVC's debugger, it thinks it's a MOVD
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arg.operandReg = dest;
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Write8(0x66);
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arg.WriteRex(true);
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Write8(0x0f);
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Write8(0x6E);
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arg.WriteRest(0);
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} else {
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arg.operandReg = dest;
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arg.WriteRex(false);
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Write8(0xF3);
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Write8(0x0f);
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Write8(0x7E);
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arg.WriteRest(0);
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}
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}
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void MOVD_xmm(const OpArg &arg, X64Reg src) {WriteSSEOp(64, 0x7E, true, src, arg, 0);}
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void MOVQ_xmm(OpArg arg, X64Reg src) {
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if (src > 7)
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{
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// Alternate encoding
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// This does not display correctly in MSVC's debugger, it thinks it's a MOVD
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arg.operandReg = src;
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Write8(0x66);
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arg.WriteRex(true);
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Write8(0x0f);
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Write8(0x7E);
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arg.WriteRest(0);
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} else {
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// INT3();
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arg.operandReg = src;
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arg.WriteRex(false);
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Write8(0x66);
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Write8(0x0f);
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Write8(0xD6);
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arg.WriteRest(0);
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}
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}
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void WriteMXCSR(OpArg arg, int ext)
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void WriteMXCSR(OpArg arg, int ext)
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{
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{
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@ -1123,12 +1171,6 @@ namespace Gen
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}
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}
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}
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}
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void MOVD_xmm(X64Reg dest, const OpArg &arg){WriteSSEOp(64, 0x6E, true, dest, arg, 0);}
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void MOVQ_xmm(X64Reg dest, const OpArg &arg){WriteSSEOp(64, 0x6E, false, dest, arg, 0);}
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void MOVD_xmm(const OpArg &arg, X64Reg src) {WriteSSEOp(64, 0x7E, true, src, arg, 0);}
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void MOVQ_xmm(const OpArg &arg, X64Reg src) {WriteSSEOp(64, 0x7E, false, src, arg, 0);}
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//There are a few more left
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//There are a few more left
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// Also some integer instrucitons are missing
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// Also some integer instrucitons are missing
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@ -1165,8 +1207,11 @@ namespace Gen
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}
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}
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void PSHUFB(X64Reg dest, OpArg arg) {
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void PSHUFB(X64Reg dest, OpArg arg) {
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INT3(); //still untested
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if (!cpu_info.bSSE3NewInstructions) {
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PanicAlert("Trying to use PSHUFB on a system that doesn't support it. Bad programmer.");
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}
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Write8(0x66);
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Write8(0x66);
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arg.operandReg = dest;
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arg.WriteRex(false);
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arg.WriteRex(false);
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Write8(0x0f);
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Write8(0x0f);
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Write8(0x38);
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Write8(0x38);
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@ -414,9 +414,9 @@ namespace Gen
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void MOVMSKPD(X64Reg dest, OpArg arg);
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void MOVMSKPD(X64Reg dest, OpArg arg);
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void MOVD_xmm(X64Reg dest, const OpArg &arg);
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void MOVD_xmm(X64Reg dest, const OpArg &arg);
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void MOVQ_xmm(X64Reg dest, const OpArg &arg);
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void MOVQ_xmm(X64Reg dest, OpArg arg);
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void MOVD_xmm(const OpArg &arg, X64Reg src);
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void MOVD_xmm(const OpArg &arg, X64Reg src);
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void MOVQ_xmm(const OpArg &arg, X64Reg src);
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void MOVQ_xmm(OpArg arg, X64Reg src);
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void MASKMOVDQU(X64Reg dest, X64Reg src);
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void MASKMOVDQU(X64Reg dest, X64Reg src);
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void LDDQU(X64Reg dest, OpArg src);
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void LDDQU(X64Reg dest, OpArg src);
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@ -46,8 +46,8 @@
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namespace Jit64 {
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namespace Jit64 {
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static double GC_ALIGNED16(psTemp[2]) = {1.0, 1.0};
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double GC_ALIGNED16(psTemp[2]) = {1.0, 1.0};
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static u64 GC_ALIGNED16(temp64);
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u64 GC_ALIGNED16(temp64);
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// TODO(ector): Improve 64-bit version
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// TODO(ector): Improve 64-bit version
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void WriteDual32(u64 value, u32 address)
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void WriteDual32(u64 value, u32 address)
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@ -139,7 +139,7 @@ void psq_st(UGeckoInstruction inst)
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MOV(32, gpr.R(a), R(ABI_PARAM2));
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MOV(32, gpr.R(a), R(ABI_PARAM2));
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CVTPD2PS(XMM0, fpr.R(s));
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CVTPD2PS(XMM0, fpr.R(s));
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SHUFPS(XMM0, R(XMM0), 1);
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SHUFPS(XMM0, R(XMM0), 1);
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MOVAPS(M(&temp64), XMM0);
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MOVQ_xmm(M(&temp64), XMM0);
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MOV(64, R(ABI_PARAM1), M(&temp64));
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MOV(64, R(ABI_PARAM1), M(&temp64));
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FixupBranch argh = J_CC(CC_NZ);
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FixupBranch argh = J_CC(CC_NZ);
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BSWAP(64, ABI_PARAM1);
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BSWAP(64, ABI_PARAM1);
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@ -170,7 +170,7 @@ void psq_st(UGeckoInstruction inst)
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CVTPD2DQ(XMM0, R(XMM0));
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CVTPD2DQ(XMM0, R(XMM0));
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PACKSSDW(XMM0, R(XMM0));
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PACKSSDW(XMM0, R(XMM0));
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PACKUSWB(XMM0, R(XMM0));
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PACKUSWB(XMM0, R(XMM0));
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MOVAPS(M(&temp64), XMM0);
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MOVD_xmm(M(&temp64), XMM0);
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MOV(16, R(ABI_PARAM1), M(&temp64));
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MOV(16, R(ABI_PARAM1), M(&temp64));
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#ifdef _M_X64
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#ifdef _M_X64
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MOV(16, MComplex(RBX, ABI_PARAM2, SCALE_1, 0), R(ABI_PARAM1));
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MOV(16, MComplex(RBX, ABI_PARAM2, SCALE_1, 0), R(ABI_PARAM1));
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