mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-02-14 00:09:24 +01:00
small build fix in debug mode, misc cleanup
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@1604 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
hrydgard
parent
4f4edc05a0
commit
f0bb8f430a
@ -189,6 +189,7 @@ namespace CPUCompare
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jo.fpAccurateFlags = true;
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jo.optimizeGatherPipe = true;
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jo.fastInterrupts = false;
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jo.accurateSinglePrecision = true;
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gpr.SetEmitter(this);
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fpr.SetEmitter(this);
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@ -328,6 +329,9 @@ namespace CPUCompare
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if (emaddress == 0)
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PanicAlert("ERROR : Trying to compile at 0. LR=%08x", LR);
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// if (emaddress == 0x800aa278)
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// DebugBreak();
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int size;
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js.isLastInstruction = false;
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js.blockStart = emaddress;
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@ -433,6 +437,7 @@ namespace CPUCompare
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CALL(thunks.ProtectFunction((void *)&GPFifo::CheckGatherPipe, 0));
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}
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if (!ops[i].skip)
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PPCTables::CompileInstruction(ops[i].inst);
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gpr.SanityCheck();
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@ -19,6 +19,14 @@
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// See comments in Jit.cpp.
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// ========================
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// Mystery: Capcom vs SNK 800aa278
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// CR flags approach:
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// * Store that "N+Z flag contains CR0" or "S+Z flag contains CR3".
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// * All flag altering instructions flush this
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// * A flush simply does a conditional write to the appropriate CRx.
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// * If flag available, branch code can become absolutely trivial.
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#ifndef _JIT_H
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#define _JIT_H
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@ -128,6 +136,7 @@ private:
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bool enableFastMem;
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bool optimizeGatherPipe;
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bool fastInterrupts;
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bool accurateSinglePrecision;
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};
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@ -70,7 +70,6 @@ using namespace Gen;
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{
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LOG(DYNA_REC, "JIT Statistics =======================");
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LOG(DYNA_REC, "Number of blocks currently: %i", numBlocks);
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LOG(DYNA_REC, "Code cache size: %i b", GetCodePtr() - codeCache);
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LOG(DYNA_REC, "======================================");
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}
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@ -14,6 +14,7 @@
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#include "../PowerPC.h"
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#include "../PPCTables.h"
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#include "../PPCAnalyst.h"
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@ -22,14 +23,11 @@
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#include "JitAsm.h"
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#include "JitRegCache.h"
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using namespace Gen;
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using namespace PowerPC;
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void RegCache::Start(PPCAnalyst::BlockRegStats &stats)
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{
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void RegCache::Start(PPCAnalyst::BlockRegStats &stats)
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{
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for (int i = 0; i < NUMXREGS; i++)
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{
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xregs[i].free = true;
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@ -57,20 +55,20 @@ using namespace PowerPC;
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}*/
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//Find top regs - preload them (load bursts ain't bad)
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//But only preload IF written OR reads >= 3
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}
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}
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// these are powerpc reg indices
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void RegCache::Lock(int p1, int p2, int p3, int p4)
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{
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// these are powerpc reg indices
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void RegCache::Lock(int p1, int p2, int p3, int p4)
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{
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locks[p1] = true;
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if (p2 != 0xFF) locks[p2] = true;
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if (p3 != 0xFF) locks[p3] = true;
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if (p4 != 0xFF) locks[p4] = true;
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}
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}
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// these are x64 reg indices
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void RegCache::LockX(int x1, int x2, int x3, int x4)
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{
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// these are x64 reg indices
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void RegCache::LockX(int x1, int x2, int x3, int x4)
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{
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if (xlocks[x1]) {
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PanicAlert("RegCache: x %i already locked!");
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}
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@ -78,27 +76,27 @@ using namespace PowerPC;
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if (x2 != 0xFF) xlocks[x2] = true;
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if (x3 != 0xFF) xlocks[x3] = true;
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if (x4 != 0xFF) xlocks[x4] = true;
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}
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}
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bool RegCache::IsFreeX(int xreg) const
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{
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bool RegCache::IsFreeX(int xreg) const
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{
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return xregs[xreg].free && !xlocks[xreg];
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}
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}
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void RegCache::UnlockAll()
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{
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void RegCache::UnlockAll()
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{
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for (int i = 0; i < 32; i++)
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locks[i] = false;
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}
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}
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void RegCache::UnlockAllX()
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{
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void RegCache::UnlockAllX()
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{
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for (int i = 0; i < NUMXREGS; i++)
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xlocks[i] = false;
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}
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}
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X64Reg RegCache::GetFreeXReg()
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{
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X64Reg RegCache::GetFreeXReg()
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{
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int aCount;
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const int *aOrder = GetAllocationOrder(aCount);
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for (int i = 0; i < aCount; i++)
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@ -127,36 +125,36 @@ using namespace PowerPC;
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//Still no dice? Die!
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_assert_msg_(DYNA_REC, 0, "Regcache ran out of regs");
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return (X64Reg) -1;
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}
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}
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void RegCache::SaveState()
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{
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void RegCache::SaveState()
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{
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memcpy(saved_locks, locks, sizeof(locks));
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memcpy(saved_xlocks, xlocks, sizeof(xlocks));
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memcpy(saved_regs, regs, sizeof(regs));
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memcpy(saved_xregs, xregs, sizeof(xregs));
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}
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}
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void RegCache::LoadState()
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{
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void RegCache::LoadState()
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{
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memcpy(xlocks, saved_xlocks, sizeof(xlocks));
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memcpy(locks, saved_locks, sizeof(locks));
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memcpy(regs, saved_regs, sizeof(regs));
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memcpy(xregs, saved_xregs, sizeof(xregs));
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}
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}
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void RegCache::FlushR(X64Reg reg)
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{
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void RegCache::FlushR(X64Reg reg)
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{
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if (reg >= NUMXREGS)
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PanicAlert("Flushing non existent reg");
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if (!xregs[reg].free)
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{
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StoreFromX64(xregs[reg].ppcReg);
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}
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}
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}
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void RegCache::SanityCheck() const
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{
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void RegCache::SanityCheck() const
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{
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for (int i = 0; i < 32; i++) {
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if (regs[i].away) {
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if (regs[i].location.IsSimpleReg()) {
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@ -170,38 +168,38 @@ using namespace PowerPC;
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}
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}
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}
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}
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}
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void RegCache::DiscardRegContentsIfCached(int preg)
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{
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void RegCache::DiscardRegContentsIfCached(int preg)
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{
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if (regs[preg].away && regs[preg].location.IsSimpleReg())
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{
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xregs[regs[preg].location.GetSimpleReg()].free = true;
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xregs[regs[preg].location.GetSimpleReg()].dirty = false;
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regs[preg].away = false;
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}
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}
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}
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void GPRRegCache::SetImmediate32(int preg, u32 immValue)
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{
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void GPRRegCache::SetImmediate32(int preg, u32 immValue)
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{
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DiscardRegContentsIfCached(preg);
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regs[preg].away = true;
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regs[preg].location = Imm32(immValue);
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}
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}
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void GPRRegCache::Start(PPCAnalyst::BlockRegStats &stats)
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{
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void GPRRegCache::Start(PPCAnalyst::BlockRegStats &stats)
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{
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RegCache::Start(stats);
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}
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}
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void FPURegCache::Start(PPCAnalyst::BlockRegStats &stats)
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{
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void FPURegCache::Start(PPCAnalyst::BlockRegStats &stats)
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{
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RegCache::Start(stats);
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}
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}
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const int *GPRRegCache::GetAllocationOrder(int &count)
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{
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const int *GPRRegCache::GetAllocationOrder(int &count)
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{
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static const int allocationOrder[] =
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{
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#ifdef _M_X64
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@ -216,10 +214,10 @@ using namespace PowerPC;
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};
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count = sizeof(allocationOrder) / sizeof(const int);
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return allocationOrder;
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}
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}
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const int *FPURegCache::GetAllocationOrder(int &count)
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{
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const int *FPURegCache::GetAllocationOrder(int &count)
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{
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static const int allocationOrder[] =
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{
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#ifdef _M_X64
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@ -230,28 +228,28 @@ using namespace PowerPC;
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};
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count = sizeof(allocationOrder) / sizeof(int);
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return allocationOrder;
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}
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}
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OpArg GPRRegCache::GetDefaultLocation(int reg) const
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{
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OpArg GPRRegCache::GetDefaultLocation(int reg) const
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{
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return M(&ppcState.gpr[reg]);
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}
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}
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OpArg FPURegCache::GetDefaultLocation(int reg) const
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{
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OpArg FPURegCache::GetDefaultLocation(int reg) const
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{
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return M(&ppcState.ps[reg][0]);
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}
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}
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void RegCache::KillImmediate(int preg)
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{
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void RegCache::KillImmediate(int preg)
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{
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if (regs[preg].away && regs[preg].location.IsImm())
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{
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LoadToX64(preg, true, true);
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}
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}
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}
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void GPRRegCache::LoadToX64(int i, bool doLoad, bool makeDirty)
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{
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void GPRRegCache::LoadToX64(int i, bool doLoad, bool makeDirty)
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{
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if (!regs[i].away && regs[i].location.IsImm())
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PanicAlert("Bad immedaite");
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@ -285,10 +283,10 @@ using namespace PowerPC;
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if (xlocks[RX(i)]) {
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PanicAlert("Seriously WTF, this reg should have been flushed");
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}
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}
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}
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void GPRRegCache::StoreFromX64(int i)
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{
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void GPRRegCache::StoreFromX64(int i)
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{
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if (regs[i].away)
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{
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bool doStore;
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@ -311,10 +309,10 @@ using namespace PowerPC;
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regs[i].location = newLoc;
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regs[i].away = false;
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}
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}
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}
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void FPURegCache::LoadToX64(int i, bool doLoad, bool makeDirty)
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{
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void FPURegCache::LoadToX64(int i, bool doLoad, bool makeDirty)
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{
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_assert_msg_(DYNA_REC, !regs[i].location.IsImm(), "WTF - load - imm");
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if (!regs[i].away)
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{
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@ -339,10 +337,10 @@ using namespace PowerPC;
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// There are no immediates in the FPR reg file, so we already had this in a register. Make dirty as necessary.
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xregs[RX(i)].dirty |= makeDirty;
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}
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}
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}
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void FPURegCache::StoreFromX64(int i)
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{
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void FPURegCache::StoreFromX64(int i)
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{
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_assert_msg_(DYNA_REC, !regs[i].location.IsImm(), "WTF - store - imm");
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if (regs[i].away)
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{
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@ -360,10 +358,10 @@ using namespace PowerPC;
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{
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// _assert_msg_(DYNA_REC,0,"already stored");
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}
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}
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}
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void RegCache::Flush(FlushMode mode)
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{
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void RegCache::Flush(FlushMode mode)
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{
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for (int i = 0; i < NUMXREGS; i++) {
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if (xlocks[i])
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PanicAlert("Somone forgot to unlock X64 reg %i.", i);
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@ -392,4 +390,4 @@ using namespace PowerPC;
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}
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}
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}
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}
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}
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@ -20,34 +20,34 @@
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#include "x64Emitter.h"
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using namespace Gen;
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enum FlushMode
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{
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using namespace Gen;
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enum FlushMode
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{
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FLUSH_ALL
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};
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};
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enum GrabMode
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{
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enum GrabMode
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{
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M_READ = 1,
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M_WRITE = 2,
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M_READWRITE = 3,
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};
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};
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struct PPCCachedReg
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{
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struct PPCCachedReg
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{
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OpArg location;
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bool away; // value not in source register
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};
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};
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struct X64CachedReg
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{
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struct X64CachedReg
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{
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int ppcReg;
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bool dirty;
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bool free;
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};
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};
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typedef int XReg;
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typedef int PReg;
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typedef int XReg;
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typedef int PReg;
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#ifdef _M_X64
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#define NUMXREGS 16
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@ -55,14 +55,14 @@
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#define NUMXREGS 8
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#endif
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class RegCache
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{
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private:
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class RegCache
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{
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private:
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bool locks[32];
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bool saved_locks[32];
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bool saved_xlocks[NUMXREGS];
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protected:
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protected:
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bool xlocks[NUMXREGS];
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PPCCachedReg regs[32];
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X64CachedReg xregs[NUMXREGS];
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@ -75,7 +75,7 @@
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XEmitter *emit;
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public:
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public:
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virtual ~RegCache() {}
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virtual void Start(PPCAnalyst::BlockRegStats &stats) = 0;
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@ -123,29 +123,28 @@
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void SaveState();
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void LoadState();
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};
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};
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class GPRRegCache : public RegCache
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{
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public:
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class GPRRegCache : public RegCache
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{
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public:
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void Start(PPCAnalyst::BlockRegStats &stats);
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void LoadToX64(int preg, bool doLoad = true, bool makeDirty = true);
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void StoreFromX64(int preg);
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OpArg GetDefaultLocation(int reg) const;
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const int *GetAllocationOrder(int &count);
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void SetImmediate32(int preg, u32 immValue);
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};
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};
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class FPURegCache : public RegCache
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{
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public:
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class FPURegCache : public RegCache
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{
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public:
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void Start(PPCAnalyst::BlockRegStats &stats);
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void LoadToX64(int preg, bool doLoad = true, bool makeDirty = true);
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void StoreFromX64(int preg);
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const int *GetAllocationOrder(int &count);
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OpArg GetDefaultLocation(int reg) const;
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};
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};
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#endif
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@ -202,6 +202,7 @@
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if (!merge_branch) {
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// Keep the normal code separate for clarity.
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CMP(32, gpr.R(a), comparand);
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FixupBranch pLesser = J_CC(less_than);
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FixupBranch pGreater = J_CC(greater_than);
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MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x2)); // _x86Reg == 0
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@ -216,42 +217,45 @@
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} else {
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int test_bit = 8 >> (js.next_inst.BI & 3);
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bool condition = (js.next_inst.BO & 8) ? false : true;
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u32 destination;
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if (js.next_inst.AA)
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destination = SignExt16(js.next_inst.BD << 2);
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else
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destination = js.next_compilerPC + SignExt16(js.next_inst.BD << 2);
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CMP(32, gpr.R(a), comparand);
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gpr.UnlockAll();
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u32 destination1;
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if (js.next_inst.AA)
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destination1 = SignExt16(js.next_inst.BD << 2);
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else
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destination1 = js.next_compilerPC + SignExt16(js.next_inst.BD << 2);
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u32 destination2 = js.next_compilerPC + 4;
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// Test swapping (in the future, will be used to inline across branches the right way)
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// if (rand() & 1)
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// std::swap(destination1, destination2), condition = !condition;
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||||
|
||||
gpr.Flush(FLUSH_ALL);
|
||||
fpr.Flush(FLUSH_ALL);
|
||||
FixupBranch pLesser = J_CC(less_than);
|
||||
FixupBranch pGreater = J_CC(greater_than);
|
||||
MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x2)); // _x86Reg == 0
|
||||
MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x2)); // == 0
|
||||
FixupBranch continue1 = J();
|
||||
|
||||
SetJumpTarget(pGreater);
|
||||
MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x4)); // _x86Reg > 0
|
||||
MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x4)); // > 0
|
||||
FixupBranch continue2 = J();
|
||||
|
||||
SetJumpTarget(pLesser);
|
||||
MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x8)); // _x86Reg < 0
|
||||
MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x8)); // < 0
|
||||
FixupBranch continue3;
|
||||
if (!!(8 & test_bit) == condition) continue3 = J();
|
||||
|
||||
//if (!!(8 & test_bit) != condition) SetJumpTarget(continue3);
|
||||
if (!!(4 & test_bit) != condition) SetJumpTarget(continue2);
|
||||
if (!!(2 & test_bit) != condition) SetJumpTarget(continue1);
|
||||
|
||||
WriteExit(destination, 0);
|
||||
WriteExit(destination1, 0);
|
||||
|
||||
if (!!(8 & test_bit) == condition) SetJumpTarget(continue3);
|
||||
if (!!(4 & test_bit) == condition) SetJumpTarget(continue2);
|
||||
if (!!(2 & test_bit) == condition) SetJumpTarget(continue1);
|
||||
|
||||
WriteExit(js.next_compilerPC + 4, 1);
|
||||
WriteExit(destination2, 1);
|
||||
|
||||
js.cancel = true;
|
||||
}
|
||||
|
||||
@ -139,11 +139,18 @@ void Jit64::WriteFloatToConstRamAddress(const Gen::X64Reg& xmm_reg, u32 address)
|
||||
|
||||
void Jit64::ForceSinglePrecisionS(X64Reg xmm) {
|
||||
// Most games don't need these. Zelda requires it though - some platforms get stuck without them.
|
||||
if (jo.accurateSinglePrecision)
|
||||
{
|
||||
CVTSD2SS(xmm, R(xmm));
|
||||
CVTSS2SD(xmm, R(xmm));
|
||||
}
|
||||
}
|
||||
|
||||
void Jit64::ForceSinglePrecisionP(X64Reg xmm) {
|
||||
// Most games don't need these. Zelda requires it though - some platforms get stuck without them.
|
||||
if (jo.accurateSinglePrecision)
|
||||
{
|
||||
CVTPD2PS(xmm, R(xmm));
|
||||
CVTPS2PD(xmm, R(xmm));
|
||||
}
|
||||
}
|
||||
|
||||
@ -313,6 +313,7 @@ bool Flatten(u32 address, int *realsize, BlockStats *st, BlockRegStats *gpa, Blo
|
||||
code[i].inst = inst;
|
||||
code[i].branchTo = -1;
|
||||
code[i].branchToIndex = -1;
|
||||
code[i].skip = false;
|
||||
GekkoOPInfo *opinfo = GetOpInfo(inst);
|
||||
if (opinfo)
|
||||
numCycles += opinfo->numCyclesMinusOne + 1;
|
||||
@ -345,6 +346,7 @@ bool Flatten(u32 address, int *realsize, BlockStats *st, BlockRegStats *gpa, Blo
|
||||
}
|
||||
else
|
||||
{
|
||||
code[i].skip = true;
|
||||
address = destination;
|
||||
}
|
||||
}
|
||||
|
||||
@ -49,6 +49,7 @@ struct CodeOp //16B
|
||||
bool outputCR0;
|
||||
bool outputCR1;
|
||||
bool outputPS1;
|
||||
bool skip; // followed BL-s for example
|
||||
};
|
||||
|
||||
struct BlockStats
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user