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Got the games to try and send out a packet. Probably something to do with DHCP. If I want to go any farther, I need to create the virtual network interface now

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git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3207 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Sonicadvance1 2009-05-11 22:37:53 +00:00
parent 5f55d4e7f0
commit f16d0d1998
2 changed files with 60 additions and 16 deletions
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60
Source/Core/Core/Src/HW/EXI_DeviceEthernet.cpp
View File

@ -23,7 +23,7 @@
#include "EXI_Device.h" #include "EXI_Device.h"
#include "EXI_DeviceEthernet.h" #include "EXI_DeviceEthernet.h"
//#define SONICDEBUG #define SONICDEBUG
void DEBUGPRINT (const char * format, ...) void DEBUGPRINT (const char * format, ...)
{ {
@ -78,6 +78,7 @@ CEXIETHERNET::CEXIETHERNET() :
mReadP = INVALID_P; mReadP = INVALID_P;
mReadyToSend = false; mReadyToSend = false;
Activated = false; Activated = false;
m_bInterruptSet = false;
mRecvBufferLength = 0; mRecvBufferLength = 0;
@ -85,6 +86,7 @@ CEXIETHERNET::CEXIETHERNET() :
Expecting = EXPECT_NONE; Expecting = EXPECT_NONE;
mExpectVariableLengthImmWrite = false; mExpectVariableLengthImmWrite = false;
mBbaMem[BBA_NWAYS] = (BBA_NWAYS_LS10 | BBA_NWAYS_LPNWAY | BBA_NWAYS_ANCLPT | BBA_NWAYS_10TXF);
} }
void CEXIETHERNET::SetCS(int cs) void CEXIETHERNET::SetCS(int cs)
@ -114,7 +116,7 @@ void CEXIETHERNET::Update()
} }
bool CEXIETHERNET::IsInterruptSet() bool CEXIETHERNET::IsInterruptSet()
{ {
return false; return m_bInterruptSet;
} }
void CEXIETHERNET::recordSendComplete() void CEXIETHERNET::recordSendComplete()
@ -123,8 +125,9 @@ void CEXIETHERNET::recordSendComplete()
if(mBbaMem[0x08] & BBA_INTERRUPT_SENT) if(mBbaMem[0x08] & BBA_INTERRUPT_SENT)
{ {
mBbaMem[0x09] |= BBA_INTERRUPT_SENT; mBbaMem[0x09] |= BBA_INTERRUPT_SENT;
DEBUGPRINT( "BBA Send interrupt raised\n"); DEBUGPRINT( "\t\tBBA Send interrupt raised\n");
exit(0); //exit(0);
m_bInterruptSet = true;
//interrupt.raiseEXI("BBA Send"); //interrupt.raiseEXI("BBA Send");
} }
mPacketsSent++; mPacketsSent++;
@ -170,8 +173,16 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
DEBUGPRINT( "IMM Write, size 0x%x, data 0x%x mWriteP 0x%x\n", _uSize, _uData, mWriteP); DEBUGPRINT( "IMM Write, size 0x%x, data 0x%x mWriteP 0x%x\n", _uSize, _uData, mWriteP);
if (mExpectVariableLengthImmWrite) if (mExpectVariableLengthImmWrite)
{ {
DEBUGPRINT( "Not doing expecting variable length imm write!\n"); if(_uSize == 4)
exit(0); {
_uData = Common::swap32(_uData);
}
else if(_uSize == 2)
{
_uData = Common::swap16(_uData);
}
mWriteBuffer.write(_uSize, &_uData);
return;
} }
else if (mWriteP != INVALID_P) else if (mWriteP != INVALID_P)
{ {
@ -184,15 +195,16 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
switch (mWriteP) switch (mWriteP)
{ {
case 0x09: case BBA_IR:
{ {
//BBADEGUB("BBA Interrupt reset 0x%02X & ~(0x%02X) => 0x%02X\n", mBbaMem[0x09], MAKE(BYTE, data), mBbaMem[0x09] & ~MAKE(BYTE, data)); //BBADEGUB("BBA Interrupt reset 0x%02X & ~(0x%02X) => 0x%02X\n", mBbaMem[0x09], MAKE(BYTE, data), mBbaMem[0x09] & ~MAKE(BYTE, data));
//assert(_uSize == 1); //assert(_uSize == 1);
// TODO: Should we swap our data? // TODO: Should we swap our data?
// With _uData not swapped, it becomes 0 when the data is 0xff000000 // With _uData not swapped, it becomes 0 when the data is 0xff000000
// With _uData swapped, it becomes 0 as well. Who knows the right way? // With _uData swapped, it becomes 0 as well. Who knows the right way?
u32 SwappedData = Common::swap32(_uData); //u32 SwappedData = Common::swap32(_uData);
mBbaMem[0x09] &= ~MAKE(u8, SwappedData); u32 SwappedData = _uData;
mBbaMem[BBA_IR] &= ~MAKE(u8, SwappedData);
DEBUGPRINT( "\t[INFO]mWriteP is %x. mBbaMem[0x09] is 0x%x\n", mWriteP, mBbaMem[0x09]); DEBUGPRINT( "\t[INFO]mWriteP is %x. mBbaMem[0x09] is 0x%x\n", mWriteP, mBbaMem[0x09]);
//exit(0); //exit(0);
break; break;
@ -239,11 +251,10 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
activate(); activate();
//say we've successfully negotiated for 10 Mbit full duplex //say we've successfully negotiated for 10 Mbit full duplex
//should placate libogc //should placate libogc
mBbaMem[BBA_NWAYS] = BBA_NWAYS_LS10 | BBA_NWAYS_LPNWAY | mBbaMem[BBA_NWAYS] = (BBA_NWAYS_LS10 | BBA_NWAYS_LPNWAY |BBA_NWAYS_ANCLPT | BBA_NWAYS_10TXF);
BBA_NWAYS_ANCLPT | BBA_NWAYS_10TXF;
} }
break; break;
case 0x18: //RRP - Receive Buffer Read Page Pointer case BBA_RRP: //RRP - Receive Buffer Read Page Pointer
DEBUGPRINT( "\t[INFO]RRP\n"); DEBUGPRINT( "\t[INFO]RRP\n");
//exit(0); //exit(0);
assert(_uSize == 2 || _uSize == 1); assert(_uSize == 2 || _uSize == 1);
@ -251,12 +262,17 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
mRBEmpty = mRBRPP == ((u32)mCbw.p_write() + CB_OFFSET); mRBEmpty = mRBRPP == ((u32)mCbw.p_write() + CB_OFFSET);
checkRecvBuffer(); checkRecvBuffer();
break; break;
case 0x16: //RWP - Receive Buffer Write Page Pointer case BBA_RWP: //RWP - Receive Buffer Write Page Pointer
DEBUGPRINT( "\t[INFO]RWP\n"); DEBUGPRINT( "\t[INFO]RWP\n");
//exit(0); //exit(0);
/*MYASSERT(size == 2 || size == 1); /*MYASSERT(size == 2 || size == 1);
MYASSERT(data == DWORD((WORD)mCbw.p_write() + CB_OFFSET) >> 8);*/ MYASSERT(data == DWORD((WORD)mCbw.p_write() + CB_OFFSET) >> 8);*/
break; break;
case BBA_NWAYS:
DEBUGPRINT(" Call to BBA_NWAYS directly!\n");
exit(0);
break;
case BBA_SI_ACTRL2:
default: default:
DEBUGPRINT( "\t[INFO]Default one!Size 0x%x _uData: 0x%08x Swapped 0x%08x to 0x%x\n", _uSize, _uData, Common::swap32(_uData),mWriteP); DEBUGPRINT( "\t[INFO]Default one!Size 0x%x _uData: 0x%08x Swapped 0x%08x to 0x%x\n", _uSize, _uData, Common::swap32(_uData),mWriteP);
//u32 SwappedData = Common::swap32(_uData); //u32 SwappedData = Common::swap32(_uData);
@ -389,9 +405,12 @@ u32 CEXIETHERNET::ImmRead(u32 _uSize)
} }
u32 uResult = 0; u32 uResult = 0;
memcpy(&uResult, mBbaMem + mReadP, _uSize); memcpy(&uResult, mBbaMem + mReadP, _uSize);
if(mReadP == 0x31)
uResult = (BBA_NWAYS_LS10 | BBA_NWAYS_LPNWAY |BBA_NWAYS_ANCLPT | BBA_NWAYS_10TXF);
// TODO: We do as well? // TODO: We do as well?
uResult = Common::swap32(uResult); //Whinecube : we have a byteswap problem... uResult = Common::swap32(uResult); //Whinecube : we have a byteswap problem...
//DEBUGPRINT("Mem spot is 0x%02x uResult is 0x%x\n", mBbaMem[mReadP], uResult);
DEBUGPRINT( "\t[INFO]Read from BBA address 0x%0*X, %i byte%s: 0x%0*X\n",mReadP >= CB_OFFSET ? 4 : 2, mReadP, _uSize, (_uSize==1?"":"s"),_uSize*2, getbitsw(uResult, 0, _uSize * 8 - 1)); DEBUGPRINT( "\t[INFO]Read from BBA address 0x%0*X, %i byte%s: 0x%0*X\n",mReadP >= CB_OFFSET ? 4 : 2, mReadP, _uSize, (_uSize==1?"":"s"),_uSize*2, getbitsw(uResult, 0, _uSize * 8 - 1));
mReadP = mReadP + _uSize; mReadP = mReadP + _uSize;
return uResult; return uResult;
@ -406,8 +425,19 @@ u32 CEXIETHERNET::ImmRead(u32 _uSize)
void CEXIETHERNET::DMAWrite(u32 _uAddr, u32 _uSize) void CEXIETHERNET::DMAWrite(u32 _uAddr, u32 _uSize)
{ {
DEBUGPRINT( "DMAW\n"); if(mExpectVariableLengthImmWrite)
{
DEBUGPRINT("Address is 0x%x and size is 0x%x\n", _uAddr, _uSize);
mWriteBuffer.write(_uSize, Memory::GetPointer(_uAddr));
return;
}
else
{
DEBUGPRINT("Unhandled BBA DMA write: %i, 0x%08X\n", _uSize, _uAddr);
//if(g::bouehr)
exit(0); exit(0);
//return EXI_UNHANDLED;
}
} }
void CEXIETHERNET::DMARead(u32 _uAddr, u32 _uSize) void CEXIETHERNET::DMARead(u32 _uAddr, u32 _uSize)

14
Source/Core/Core/Src/HW/EXI_DeviceEthernet.h
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@ -82,6 +82,7 @@ private:
u32 m_uPosition; u32 m_uPosition;
u32 m_uCommand; u32 m_uCommand;
bool m_bInterruptSet;
u32 mWriteP, mReadP; u32 mWriteP, mReadP;
#define INVALID_P 0xFFFF #define INVALID_P 0xFFFF
@ -149,6 +150,16 @@ enum{
BBA_NCRB_4_PACKETS_PER_INT = (2<<6), /* 1 0 */ BBA_NCRB_4_PACKETS_PER_INT = (2<<6), /* 1 0 */
BBA_NCRB_8_PACKETS_PER_INT = (3<<6), /* 1 1 */ BBA_NCRB_8_PACKETS_PER_INT = (3<<6), /* 1 1 */
BBA_IR = 0x09, /* Interrupt Register, RW, 00h */
BBA_IR_FRAGI = (1<<0), /* FRAGI, Fragment Counter Interrupt */
BBA_IR_RI = (1<<1), /* RI, Receive Interrupt */
BBA_IR_TI = (1<<2), /* TI, Transmit Interrupt */
BBA_IR_REI = (1<<3), /* REI, Receive Error Interrupt */
BBA_IR_TEI = (1<<4), /* TEI, Transmit Error Interrupt */
BBA_IR_FIFOEI = (1<<5), /* FIFOEI, FIFO Error Interrupt */
BBA_IR_BUSEI = (1<<6), /* BUSEI, BUS Error Interrupt */
BBA_IR_RBFI = (1<<7), /* RBFI, RX Buffer Full Interrupt */
BBA_NWAYC = 0x30, /* NWAY Configuration Register, RW, 84h */ BBA_NWAYC = 0x30, /* NWAY Configuration Register, RW, 84h */
BBA_NWAYC_FD = (1<<0), /* FD, Full Duplex Mode */ BBA_NWAYC_FD = (1<<0), /* FD, Full Duplex Mode */
BBA_NWAYC_PS100 = (1<<1), /* PS100/10, Port Select 100/10 */ BBA_NWAYC_PS100 = (1<<1), /* PS100/10, Port Select 100/10 */
@ -169,6 +180,9 @@ enum{
BBA_INTERRUPT_SENT = 0x04, BBA_INTERRUPT_SENT = 0x04,
BBA_INTERRUPT_RECV_ERROR = 0x08, BBA_INTERRUPT_RECV_ERROR = 0x08,
BBA_INTERRUPT_SEND_ERROR = 0x10, BBA_INTERRUPT_SEND_ERROR = 0x10,
BBA_RWP = 0x16, /* Receive Buffer Write Page Pointer Register */
BBA_RRP = 0x18, /* Receive Buffer Read Page Pointer Register */
BBA_SI_ACTRL2 = 0x60,
}; };
#endif #endif