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https://github.com/dolphin-emu/dolphin.git
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Remove x86_32 from Jit64IL.
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1d5281068d
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@ -137,7 +137,6 @@ static void fregSpill(RegInfo& RI, X64Reg reg) {
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}
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}
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// ECX is scratch, so we don't allocate it
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// ECX is scratch, so we don't allocate it
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#if _M_X86_64
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// 64-bit - calling conventions differ between linux & windows, so...
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// 64-bit - calling conventions differ between linux & windows, so...
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#ifdef _WIN32
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#ifdef _WIN32
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@ -149,16 +148,6 @@ static const int RegAllocSize = sizeof(RegAllocOrder) / sizeof(X64Reg);
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static const X64Reg FRegAllocOrder[] = {XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, XMM2, XMM3, XMM4, XMM5};
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static const X64Reg FRegAllocOrder[] = {XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, XMM2, XMM3, XMM4, XMM5};
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static const int FRegAllocSize = sizeof(FRegAllocOrder) / sizeof(X64Reg);
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static const int FRegAllocSize = sizeof(FRegAllocOrder) / sizeof(X64Reg);
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#else
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// 32-bit
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static const X64Reg RegAllocOrder[] = {EDI, ESI, EBP, EBX, EDX, EAX};
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static const int RegAllocSize = sizeof(RegAllocOrder) / sizeof(X64Reg);
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static const X64Reg FRegAllocOrder[] = {XMM2, XMM3, XMM4, XMM5, XMM6, XMM7};
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static const int FRegAllocSize = sizeof(FRegAllocOrder) / sizeof(X64Reg);
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#endif
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static X64Reg regFindFreeReg(RegInfo& RI) {
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static X64Reg regFindFreeReg(RegInfo& RI) {
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for (auto& reg : RegAllocOrder)
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for (auto& reg : RegAllocOrder)
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if (RI.regs[reg] == nullptr)
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if (RI.regs[reg] == nullptr)
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@ -256,13 +245,6 @@ static X64Reg fregEnsureInReg(RegInfo& RI, InstLoc I) {
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}
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}
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static void regSpillCallerSaved(RegInfo& RI) {
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static void regSpillCallerSaved(RegInfo& RI) {
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#if _M_X86_32
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// 32-bit
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regSpill(RI, EDX);
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regSpill(RI, ECX);
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regSpill(RI, EAX);
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#else
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// 64-bit
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regSpill(RI, RCX);
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regSpill(RI, RCX);
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regSpill(RI, RDX);
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regSpill(RI, RDX);
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regSpill(RI, RSI);
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regSpill(RI, RSI);
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@ -271,7 +253,6 @@ static void regSpillCallerSaved(RegInfo& RI) {
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regSpill(RI, R9);
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regSpill(RI, R9);
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regSpill(RI, R10);
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regSpill(RI, R10);
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regSpill(RI, R11);
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regSpill(RI, R11);
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#endif
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}
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}
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static X64Reg regUReg(RegInfo& RI, InstLoc I) {
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static X64Reg regUReg(RegInfo& RI, InstLoc I) {
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@ -1292,13 +1273,9 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress) {
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Jit->MOVZX(32, 16, EAX, M(((char *)&GQR(quantreg)) + 2));
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Jit->MOVZX(32, 16, EAX, M(((char *)&GQR(quantreg)) + 2));
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Jit->MOVZX(32, 8, EDX, R(AL));
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Jit->MOVZX(32, 8, EDX, R(AL));
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Jit->OR(32, R(EDX), Imm8(w << 3));
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Jit->OR(32, R(EDX), Imm8(w << 3));
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#if _M_X86_32
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int addr_scale = SCALE_4;
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#else
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int addr_scale = SCALE_8;
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#endif
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Jit->MOV(32, R(ECX), regLocForInst(RI, getOp1(I)));
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Jit->MOV(32, R(ECX), regLocForInst(RI, getOp1(I)));
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Jit->CALLptr(MScaled(EDX, addr_scale, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedLoadQuantized)));
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Jit->CALLptr(MScaled(EDX, SCALE_8, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedLoadQuantized)));
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Jit->MOVAPD(reg, R(XMM0));
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Jit->MOVAPD(reg, R(XMM0));
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RI.fregs[reg] = I;
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RI.fregs[reg] = I;
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regNormalRegClear(RI, I);
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regNormalRegClear(RI, I);
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@ -1342,14 +1319,10 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress) {
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u32 quantreg = *I >> 24;
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u32 quantreg = *I >> 24;
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Jit->MOVZX(32, 16, EAX, M(&PowerPC::ppcState.spr[SPR_GQR0 + quantreg]));
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Jit->MOVZX(32, 16, EAX, M(&PowerPC::ppcState.spr[SPR_GQR0 + quantreg]));
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Jit->MOVZX(32, 8, EDX, R(AL));
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Jit->MOVZX(32, 8, EDX, R(AL));
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#if _M_X86_32
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int addr_scale = SCALE_4;
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#else
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int addr_scale = SCALE_8;
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#endif
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Jit->MOV(32, R(ECX), regLocForInst(RI, getOp2(I)));
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Jit->MOV(32, R(ECX), regLocForInst(RI, getOp2(I)));
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Jit->MOVAPD(XMM0, fregLocForInst(RI, getOp1(I)));
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Jit->MOVAPD(XMM0, fregLocForInst(RI, getOp1(I)));
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Jit->CALLptr(MScaled(EDX, addr_scale, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedStoreQuantized)));
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Jit->CALLptr(MScaled(EDX, SCALE_8, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedStoreQuantized)));
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if (RI.IInfo[I - RI.FirstI] & 4)
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if (RI.IInfo[I - RI.FirstI] & 4)
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fregClearInst(RI, getOp1(I));
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fregClearInst(RI, getOp1(I));
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if (RI.IInfo[I - RI.FirstI] & 8)
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if (RI.IInfo[I - RI.FirstI] & 8)
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@ -1831,12 +1804,8 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress) {
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Jit->OR(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_ISI));
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Jit->OR(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_ISI));
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// Remove the invalid instruction from the icache, forcing a recompile
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// Remove the invalid instruction from the icache, forcing a recompile
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#if _M_X86_32
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Jit->MOV(32, M(jit->GetBlockCache()->GetICachePtr(InstLoc)), Imm32(JIT_ICACHE_INVALID_WORD));
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#else
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Jit->MOV(64, R(RAX), ImmPtr(jit->GetBlockCache()->GetICachePtr(InstLoc)));
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Jit->MOV(64, R(RAX), ImmPtr(jit->GetBlockCache()->GetICachePtr(InstLoc)));
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Jit->MOV(32, MatR(RAX), Imm32(JIT_ICACHE_INVALID_WORD));
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Jit->MOV(32, MatR(RAX), Imm32(JIT_ICACHE_INVALID_WORD));
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#endif
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Jit->WriteExceptionExit();
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Jit->WriteExceptionExit();
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break;
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break;
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}
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}
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@ -346,11 +346,7 @@ static void ImHere()
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{
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{
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if (!f)
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if (!f)
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{
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{
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#if _M_X86_64
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f.Open("log64.txt", "w");
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f.Open("log64.txt", "w");
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#else
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f.Open("log32.txt", "w");
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#endif
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}
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}
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fprintf(f.GetHandle(), "%08x r0: %08x r5: %08x r6: %08x\n", PC, PowerPC::ppcState.gpr[0],
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fprintf(f.GetHandle(), "%08x r0: %08x r5: %08x r6: %08x\n", PC, PowerPC::ppcState.gpr[0],
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PowerPC::ppcState.gpr[5], PowerPC::ppcState.gpr[6]);
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PowerPC::ppcState.gpr[5], PowerPC::ppcState.gpr[6]);
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@ -36,7 +36,6 @@
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#include "Core/PowerPC/JitILCommon/IR.h"
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#include "Core/PowerPC/JitILCommon/IR.h"
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#include "Core/PowerPC/JitILCommon/JitILBase.h"
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#include "Core/PowerPC/JitILCommon/JitILBase.h"
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class JitIL : public JitILBase, public EmuCodeBlock
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class JitIL : public JitILBase, public EmuCodeBlock
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{
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{
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private:
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private:
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