From f333c0949fb95a9d3e0ad49f9f1852c9ad6068f3 Mon Sep 17 00:00:00 2001 From: JosJuice Date: Mon, 26 Jul 2021 17:48:47 +0200 Subject: [PATCH] PowerPC: Implement PI interrupt for uncached unaligned writes --- Source/Core/Core/PowerPC/MMU.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Source/Core/Core/PowerPC/MMU.cpp b/Source/Core/Core/PowerPC/MMU.cpp index 50bc648726..3c70a5319c 100644 --- a/Source/Core/Core/PowerPC/MMU.cpp +++ b/Source/Core/Core/PowerPC/MMU.cpp @@ -18,6 +18,7 @@ #include "Core/HW/GPFifo.h" #include "Core/HW/MMIO.h" #include "Core/HW/Memmap.h" +#include "Core/HW/ProcessorInterface.h" #include "Core/PowerPC/JitInterface.h" #include "Core/PowerPC/PowerPC.h" @@ -368,6 +369,11 @@ static void WriteToHardware(u32 em_address, const u32 data, const u32 size) // behavior for write-through/cache-inhibited writes with a start address or end address that // isn't 32-bit aligned. See https://bugs.dolphin-emu.org/issues/12565 for details. + // TODO: This interrupt is supposed to have associated cause and address registers + // TODO: This should trigger the hwtest's interrupt handling, but it does not seem to + // (https://github.com/dolphin-emu/hwtests/pull/42) + ProcessorInterface::SetInterrupt(ProcessorInterface::INT_CAUSE_PI); + const u32 rotated_data = Common::RotateRight(data, ((em_address & 0x3) + size) * 8); for (u32 addr = em_address & ~0x7; addr < em_address + size; addr += 8)