diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp
index fe16c5966e..500fc0fb0a 100644
--- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp
+++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp
@@ -82,6 +82,7 @@ s8 GetMultiplyModifier()
 	return(2);
 }
 
+// TODO add case comments
 bool CheckCondition(u8 _Condition)
 {
 	bool taken = false;
@@ -166,7 +167,7 @@ bool CheckCondition(u8 _Condition)
 		break;
 
 	default:
-		// DEBUG_LOG(DSPHLE, "Unknown condition check: 0x%04x\n", _Condition & 0xf);
+		ERROR_LOG(DSPHLE, "Unknown condition check: 0x%04x\n", _Condition & 0xf);
 		break;
 	}
 
@@ -178,7 +179,7 @@ bool CheckCondition(u8 _Condition)
 void unknown(const UDSPInstruction& opc)
 {
 	//_assert_msg_(MASTER_LOG, !g_dsp.exception_in_progress_hack, "assert while exception");
-	ERROR_LOG(DSPHLE, "LLE: Unrecognized opcode %d", opc.hex);
+	ERROR_LOG(DSPHLE, "LLE: Unrecognized opcode 0x%04x", opc.hex);
 	//g_dsp.pc = g_dsp.err_pc;
 }
 
@@ -193,6 +194,7 @@ void call(const UDSPInstruction& opc)
 	}
 }
 
+// The code for all ifs?
 void ifcc(const UDSPInstruction& opc)
 {
 	if (!CheckCondition(opc.hex & 0xf))
@@ -201,6 +203,7 @@ void ifcc(const UDSPInstruction& opc)
 	}
 }
 
+// The code for all jumps?
 void jcc(const UDSPInstruction& opc)
 {
 	u16 dest = dsp_fetch_code();
@@ -212,6 +215,7 @@ void jcc(const UDSPInstruction& opc)
 }
 
 // FIXME inside
+// FIXME add to opcode table
 void jmpa(const UDSPInstruction& opc)
 {
 	u8 reg;
@@ -361,7 +365,7 @@ void lrr(const UDSPInstruction& opc)
 		g_dsp.r[sreg]++;
 		break;
 
-	case 0x3:
+	case 0x3: //  LRRN
 		g_dsp.r[sreg] += g_dsp.r[sreg + 4];
 		break;
 	}
@@ -406,20 +410,20 @@ void ilrr(const UDSPInstruction& opc)
 
 	switch ((opc.hex >> 2) & 0x3)
 	{
-	case 0x0: // no change
+	case 0x0: // no change (ILRR)
 		break;
 
-	case 0x1: // post decrement
+	case 0x1: // post decrement (ILRRD?)
 		g_dsp.r[reg]--;
 		break;
 
-	case 0x2: // post increment
+	case 0x2: // post increment (ILRRI)
 		g_dsp.r[reg]++;
 		break;
 
 	default:
 		// FIXME: Implement
-		ERROR_LOG(DSPHLE, "dsp_opc.hex_ilrr");
+		ERROR_LOG(DSPHLE, "Unknown ILRR: 0x%04x\n", (opc.hex >> 2) & 0x3);
 	}
 }
 
@@ -510,6 +514,7 @@ void mulcmv(const UDSPInstruction& opc)
 	ERROR_LOG(DSPHLE, "dsp_opc.hex_mulcmv ni");
 }
 
+//TODO: add to opcode table
 void cmpar(const UDSPInstruction& opc)
 {
 	u8 rreg = ((opc.hex >> 12) & 0x1) + 0x1a;
@@ -532,6 +537,7 @@ void cmp(const UDSPInstruction& opc)
 	Update_SR_Register(acc0 - acc1);
 }
 
+//TODO: add to opcode table
 void tsta(const UDSPInstruction& opc)
 {
 	u8 reg  = (opc.hex >> 11) & 0x1;
@@ -555,6 +561,7 @@ void addaxl(const UDSPInstruction& opc)
 	Update_SR_Register(acc);
 }
 
+//TODO: add to opcode table
 void addarn(const UDSPInstruction& opc)
 {
 	u8 dreg = opc.hex & 0x3;
@@ -669,6 +676,7 @@ void nx(const UDSPInstruction& opc)
 
 
 // FIXME inside
+// TODO: add to opcode table
 void andfc(const UDSPInstruction& opc)
 {
 	if (opc.hex & 0xf)
@@ -719,6 +727,7 @@ void andf(const UDSPInstruction& opc)
 }
 
 // FIXME inside
+// TODO: add to opcode table
 void subf(const UDSPInstruction& opc)
 {
 	if (opc.hex & 0xf)
@@ -911,6 +920,7 @@ void neg(const UDSPInstruction& opc)
 }
 
 // TODO: Implement
+// FIXME: add to opcode table
 void movnp(const UDSPInstruction& opc)
 {
 	// UNIMPLEMENTED
@@ -1039,6 +1049,7 @@ void asr16(const UDSPInstruction& opc)
 	Update_SR_Register(acc);
 }
 
+// TODO: add to opcode table
 void shifti(const UDSPInstruction& opc)
 {
 	// direction: left
@@ -1131,6 +1142,7 @@ void sbset(const UDSPInstruction& opc)
 
 
 // FIXME inside
+// TODO: add to opcode table
 void srbith(const UDSPInstruction& opc)
 {
 	switch ((opc.hex >> 8) & 0xf)
diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp
index 26d8f05afa..ef667b8e4b 100644
--- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp
+++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp
@@ -38,34 +38,34 @@ DSPOPCTemplate opcodes[] =
 
 	{"CALLNE",  0x02b4, 0xffff, nop, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
 
-	{"IF_0",    0x0270, 0xffff, nop, nop, 1, 0, {},},
-	{"IF_1",    0x0271, 0xffff, nop, nop, 1, 0, {},},
-	{"IF_2",    0x0272, 0xffff, nop, nop, 1, 0, {},},
-	{"IF_3",    0x0273, 0xffff, nop, nop, 1, 0, {},},
-	{"IF_E",    0x0274, 0xffff, nop, nop, 1, 0, {},},
-	{"IF_Q",    0x0275, 0xffff, nop, nop, 1, 0, {},},
-	{"IF_R",    0x027c, 0xffff, nop, nop, 1, 0, {},},
-	{"IF_Z",    0x027d, 0xffff, nop, nop, 1, 0, {},},
-	{"IF_P",    0x027f, 0xffff, nop, nop, 1, 0, {},},
+	{"IF_0",    0x0270, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {},},
+	{"IF_1",    0x0271, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {},},
+	{"IF_2",    0x0272, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {},},
+	{"IF_3",    0x0273, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {},},
+	{"IF_E",    0x0274, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {},},
+	{"IF_Q",    0x0275, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {},},
+	{"IF_R",    0x027c, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {},},
+	{"IF_Z",    0x027d, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {},},
+	{"IF_P",    0x027f, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {},},
 
-	{"JX0",	    0x0290, 0xffff, nop, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
-	{"JX1",	    0x0291, 0xffff, nop, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
-	{"JX2",	    0x0292, 0xffff, nop, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
-	{"JX3",	    0x0293, 0xffff, nop, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
-	{"JNE",	    0x0294, 0xffff, nop, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
-	{"JEQ",	    0x0295, 0xffff, nop, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
-	{"JZR",		0x029c, 0xffff, nop, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
-	{"JNZ",		0x029d, 0xffff, nop, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
-	{"JMP",		0x029f, 0xffff, nop, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
+	{"JX0",	    0x0290, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
+	{"JX1",	    0x0291, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
+	{"JX2",	    0x0292, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
+	{"JX3",	    0x0293, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
+	{"JNE",	    0x0294, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
+	{"JEQ",	    0x0295, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
+	{"JZR",		0x029c, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
+	{"JNZ",		0x029d, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
+	{"JMP",		0x029f, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}},},
 
-	{"DAR",		0x0004, 0xfffc, nop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}},},
-	{"IAR",		0x0008, 0xfffc, nop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}},},
+	{"DAR",		0x0004, 0xfffc, DSPInterpreter::dar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}},},
+	{"IAR",		0x0008, 0xfffc, DSPInterpreter::iar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}},},
 
 	{"CALLR",   0x171f, 0xff1f, nop, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}},},
 	{"JMPR",    0x170f, 0xff1f, nop, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}},},
 
-	{"SBCLR",   0x1200, 0xfff8, nop, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}},},
-	{"SBSET",   0x1300, 0xfff8, nop, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}},},
+	{"SBCLR",   0x1200, 0xfff8, DSPInterpreter::sbclr, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}},},
+	{"SBSET",   0x1300, 0xfff8, DSPInterpreter::sbset, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}},},
 
 	{"LSL",		0x1400, 0xfec0, nop, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}},},
 	{"LSR",		0x1440, 0xfec0, nop, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}},},
@@ -73,58 +73,59 @@ DSPOPCTemplate opcodes[] =
 	{"ASR",		0x14c0, 0xfec0, nop, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x007f}},},
 
 
-	{"LRI",		0x0080, 0xffe0, nop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}},},
-	{"LR",      0x00c0, 0xffe0, nop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}},},
-	{"SR",      0x00e0, 0xffe0, nop, nop, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}},},
+	{"LRI",		0x0080, 0xffe0, DSPInterpreter::lri, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}},},
+	{"LR",      0x00c0, 0xffe0, DSPInterpreter::lr, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}},},
+	{"SR",      0x00e0, 0xffe0, DSPInterpreter::sr, nop, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}},},
 
-	{"MRR",		0x1c00, 0xfc00, nop, nop, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}},},
+	{"MRR",		0x1c00, 0xfc00, DSPInterpreter::mrr, nop, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}},},
 
-	{"SI",      0x1600, 0xff00, nop, nop, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}},},
+	{"SI",      0x1600, 0xff00, DSPInterpreter::si, nop, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}},},
 
 	{"LRS",		0x2000, 0xf800, nop, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}},},
 	{"SRS",		0x2800, 0xf800, nop, nop, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}},},
 
-	{"LRIS",    0x0800, 0xf800, nop, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}},},
+	{"LRIS",    0x0800, 0xf800, DSPInterpreter::lris, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}},},
 
-	{"ADDIS",   0x0400, 0xfe00, nop, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}},},
-	{"CMPIS",   0x0600, 0xfe00, nop, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}},},
+	{"ADDIS",   0x0400, 0xfe00, DSPInterpreter::addis, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}},},
+	{"CMPIS",   0x0600, 0xfe00, DSPInterpreter::cmpis, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}},},
 
-	{"ANDI",    0x0240, 0xfeff, nop, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},},
-	{"ANDF",    0x02c0, 0xfeff, nop, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},},
+	{"ANDI",    0x0240, 0xfeff, DSPInterpreter::andi, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},},
+	{"ANDF",    0x02c0, 0xfeff, DSPInterpreter::andf, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},},
 
-	{"XORI",    0x0220, 0xfeff, nop, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},},
+	{"XORI",    0x0220, 0xfeff, DSPInterpreter::xori, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},},
 	{"ANDCF",   0x02a0, 0xfeff, nop, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},},
 
-	{"ORI",		0x0260, 0xfeff, nop, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},},
+	{"ORI",		0x0260, 0xfeff, DSPInterpreter::ori, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},},
 	{"ORF",		0x02e0, 0xfeff, nop, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},},
 
-	{"ADDI",    0x0200, 0xfeff, nop, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},}, // missing S64
+	{"ADDI",    0x0200, 0xfeff, DSPInterpreter::addi, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},}, // missing S64
 	{"CMPI",    0x0280, 0xfeff, nop, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},}, // missing S64
 
-	{"ILRR",    0x0210, 0xfedc, nop, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}},},
-	{"ILRRI",   0x0218, 0xfedc, nop, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}},},
+	{"ILRR",    0x0210, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}},},
+	{"ILRRD",    0x0214, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}},},
+	{"ILRRI",   0x0218, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}},},
 
 	// load and store value pointed by indexing reg and increment; LRR/SRR variants
-	{"LRRI",    0x1900, 0xff80, nop, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}},},
-	{"LRRD",    0x1880, 0xff80, nop, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}},},
-	{"LRRN",    0x1980, 0xff80, nop, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}},},
-	{"LRR",		0x1800, 0xff80, nop, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}},},
-	{"SRRI",    0x1b00, 0xff80, nop, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}},},
-	{"SRRD",    0x1a80, 0xff80, nop, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}},},
-	{"SRRN",    0x1b80, 0xff80, nop, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}},},
-	{"SRR",		0x1a00, 0xff80, nop, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}},},
+	{"LRRI",    0x1900, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}},},
+	{"LRRD",    0x1880, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}},},
+	{"LRRN",    0x1980, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}},},
+	{"LRR",		0x1800, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}},},
+	{"SRRI",    0x1b00, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}},},
+	{"SRRD",    0x1a80, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}},},
+	{"SRRN",    0x1b80, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}},},
+	{"SRR",		0x1a00, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}},},
 
-	{"LOOPI",   0x1000, 0xff00, nop, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}},},
-	{"BLOOPI",  0x1100, 0xff00, nop, nop, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_VAL, 2, 1, 0, 0xffff}},},
-	{"LOOP",    0x0040, 0xffe0, nop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}},},
-	{"BLOOP",   0x0060, 0xffe0, nop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_VAL, 2, 1, 0, 0xffff}},},
+	{"LOOPI",   0x1000, 0xff00, DSPInterpreter::loopi, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}},},
+	{"BLOOPI",  0x1100, 0xff00, DSPInterpreter::bloopi, nop, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_VAL, 2, 1, 0, 0xffff}},},
+	{"LOOP",    0x0040, 0xffe0, DSPInterpreter::loop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}},},
+	{"BLOOP",   0x0060, 0xffe0, DSPInterpreter::bloop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_VAL, 2, 1, 0, 0xffff}},},
 
 
 
 	// opcodes that can be extended
 	// extended opcodes, note size of opcode will be set to 0
 
-	{"NX",      0x8000, 0xffff, nop, nop, 1 | P_EXT, 0, {},},
+	{"NX",      0x8000, 0xffff, DSPInterpreter::nx, nop, 1 | P_EXT, 0, {},},
 
 	{"S40",		0x8e00, 0xffff, nop, nop, 1 | P_EXT, 0, {},},
 	{"S16",		0x8f00, 0xffff, nop, nop, 1 | P_EXT, 0, {},},
@@ -133,70 +134,71 @@ DSPOPCTemplate opcodes[] =
 	{"CLR15",   0x8c00, 0xffff, nop, nop, 1 | P_EXT, 0, {},},
 	{"SET15",   0x8d00, 0xffff, nop, nop, 1 | P_EXT, 0, {},},
 
-	{"DECM",    0x7800, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
-	{"INCM",    0x7400, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
-	{"DEC",		0x7a00, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
-	{"INC",		0x7600, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
+	{"DECM",    0x7800, 0xfeff, DSPInterpreter::decm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
+	{"INCM",    0x7400, 0xfeff, DSPInterpreter::incm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
+	{"DEC",		0x7a00, 0xfeff, DSPInterpreter::dec, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
+	{"INC",		0x7600, 0xfeff, DSPInterpreter::inc, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
 
-	{"NEG",		0x7c00, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
+	{"NEG",		0x7c00, 0xfeff, DSPInterpreter::neg, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
 
 	{"TST",		0xb100, 0xf7ff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 11, 0x0800}},},
-	{"TSTAXH",  0x8600, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}},},
-	{"CMP",		0x8200, 0xffff, nop, nop, 1 | P_EXT, 0, {},},
+	{"TSTAXH",  0x8600, 0xfeff, DSPInterpreter::tstaxh, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}},},
+	{"CMP",		0x8200, 0xffff, DSPInterpreter::cmp, nop, 1 | P_EXT, 0, {},},
+	
 	{"CMPAXH",  0xc100, 0xe7ff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}},},
 
-	{"CLR",		0x8100, 0xf7ff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 11, 0x0800}},},
-	{"CLRP",    0x8400, 0xffff, nop, nop, 1 | P_EXT, 0, {},},
+	{"CLR",		0x8100, 0xf7ff, DSPInterpreter::clr, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 11, 0x0800}},},
+	{"CLRP",    0x8400, 0xffff, DSPInterpreter::clrp, nop, 1 | P_EXT, 0, {},},
 
 	{"MOV",		0x6c00, 0xfeff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}},},
-	{"MOVAX",   0x6800, 0xfcff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}},},
-	{"MOVR",    0x6000, 0xf8ff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}},},
-	{"MOVP",    0x6e00, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
-	{"MOVPZ",   0xfe00, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
+	{"MOVAX",   0x6800, 0xfcff, DSPInterpreter::movax, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}},},
+	{"MOVR",    0x6000, 0xf8ff, DSPInterpreter::movr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}},},
+	{"MOVP",    0x6e00, 0xfeff,  DSPInterpreter::movp, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
+	{"MOVPZ",   0xfe00, 0xfeff, DSPInterpreter::movpz, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
 
-	{"ADDPAXZ", 0xf800, 0xfcff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG1A, 1, 0, 8, 0x0100}},},
-	{"ADDP",    0x4e00, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
+	{"ADDPAXZ", 0xf800, 0xfcff, DSPInterpreter::addpaxz, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG1A, 1, 0, 8, 0x0100}},},
+	{"ADDP",    0x4e00, 0xfeff, DSPInterpreter::addp, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
 
-	{"LSL16",   0xf000, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
-	{"LSR16",   0xf400, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
-	{"ASR16",   0x9100, 0xf7ff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 11, 0x0800}},},
+	{"LSL16",   0xf000, 0xfeff, DSPInterpreter::lsl16, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
+	{"LSR16",   0xf400, 0xfeff, DSPInterpreter::lsr16, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
+	{"ASR16",   0x9100, 0xf7ff, DSPInterpreter::asr16, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 11, 0x0800}},},
 
-	{"XORR",    0x3000, 0xfcff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}},},
-	{"ANDR",    0x3400, 0xfcff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}},},
-	{"ORR",		0x3800, 0xfcff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}},},
-	{"ANDC",    0x3C00, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
+	{"XORR",    0x3000, 0xfcff, DSPInterpreter::xorr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}},},
+	{"ANDR",    0x3400, 0xfcff, DSPInterpreter::andr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}},},
+	{"ORR",		0x3800, 0xfcff, DSPInterpreter::orr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}},},
+	{"ANDC",    0x3C00, 0xfeff, DSPInterpreter::andc, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
 	{"ORC",		0x3E00, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}},},
 
-	{"MULX",    0xa000, 0xe7ff, nop, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 11, 0x1000}, {P_REG19, 1, 0, 10, 0x0800}},},
-	{"MULXAC",  0xa400, 0xe6ff, nop, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x1000}, {P_REG19, 1, 0, 10, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}},},
-	{"MULXMV",  0xa600, 0xe6ff, nop, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x1000}, {P_REG19, 1, 0, 10, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}},},
-	{"MULXMVZ", 0xa200, 0xe6ff, nop, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x1000}, {P_REG19, 1, 0, 10, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}},},
+	{"MULX",    0xa000, 0xe7ff, DSPInterpreter::mulx, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 11, 0x1000}, {P_REG19, 1, 0, 10, 0x0800}},},
+	{"MULXAC",  0xa400, 0xe6ff, DSPInterpreter::mulxac, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x1000}, {P_REG19, 1, 0, 10, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}},},
+	{"MULXMV",  0xa600, 0xe6ff, DSPInterpreter::mulxmv, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x1000}, {P_REG19, 1, 0, 10, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}},},
+	{"MULXMVZ", 0xa200, 0xe6ff, DSPInterpreter::mulxmvz, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x1000}, {P_REG19, 1, 0, 10, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}},},
 
-	{"MUL",		0x9000, 0xf7ff, nop, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}},},
-	{"MULAC",   0x9400, 0xf6ff, nop, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}},},
-	{"MULMV",   0x9600, 0xf6ff, nop, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}},},
-	{"MULMVZ",  0x9200, 0xf6ff, nop, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}},},
+	{"MUL",		0x9000, 0xf7ff, DSPInterpreter::mul, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}},},
+	{"MULAC",   0x9400, 0xf6ff, DSPInterpreter::mulac, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}},},
+	{"MULMV",   0x9600, 0xf6ff, DSPInterpreter::mulmv, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}},},
+	{"MULMVZ",  0x9200, 0xf6ff, DSPInterpreter::mulmvz, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}},},
 
-	{"MULC",    0xc000, 0xe7ff, nop, nop, 1 | P_EXT, 2, {{P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 12, 0x1000}},},
-	{"MULCAC",  0xc400, 0xe6ff, nop, nop, 1 | P_EXT, 3, {{P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 12, 0x1000}, {P_ACCM, 1, 0, 8, 0x0100}},},
-	{"MULCMV",  0xc600, 0xe6ff, nop, nop, 1 | P_EXT, 3, {{P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 12, 0x1000}, {P_ACCM, 1, 0, 8, 0x0100}},},
-	{"MULCMVZ", 0xc200, 0xe6ff, nop, nop, 1 | P_EXT, 3, {{P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 12, 0x1000}, {P_ACCM, 1, 0, 8, 0x0100}},},
+	{"MULC",    0xc000, 0xe7ff, DSPInterpreter::mulc, nop, 1 | P_EXT, 2, {{P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 12, 0x1000}},},
+	{"MULCAC",  0xc400, 0xe6ff, DSPInterpreter::mulcac, nop, 1 | P_EXT, 3, {{P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 12, 0x1000}, {P_ACCM, 1, 0, 8, 0x0100}},},
+	{"MULCMV",  0xc600, 0xe6ff, DSPInterpreter::mulcmv, nop, 1 | P_EXT, 3, {{P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 12, 0x1000}, {P_ACCM, 1, 0, 8, 0x0100}},},
+	{"MULCMVZ", 0xc200, 0xe6ff, DSPInterpreter::mulcmvz, nop, 1 | P_EXT, 3, {{P_REG1A, 1, 0, 11, 0x0800}, {P_ACCM, 1, 0, 12, 0x1000}, {P_ACCM, 1, 0, 8, 0x0100}},},
 
-	{"ADDR",    0x4000, 0xf8ff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}},},
-	{"ADDAX",   0x4800, 0xfcff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}},},
+	{"ADDR",    0x4000, 0xf8ff, DSPInterpreter::addr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}},},
+	{"ADDAX",   0x4800, 0xfcff, DSPInterpreter::addax, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}},},
 	{"ADD",		0x4c00, 0xfeff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}},},
-	{"ADDAXL",  0x7000, 0xfcff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}},},
+	{"ADDAXL",  0x7000, 0xfcff, DSPInterpreter::addaxl, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}},},
 
-	{"SUBR",    0x5000, 0xf8ff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}},},
-	{"SUBAX",   0x5800, 0xfcff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}},},
-	{"SUB",		0x5c00, 0xfeff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}},},
+	{"SUBR",    0x5000, 0xf8ff, DSPInterpreter::subr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}},},
+	{"SUBAX",   0x5800, 0xfcff, DSPInterpreter::subax, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}},},
+	{"SUB",		0x5c00, 0xfeff, DSPInterpreter::sub, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}},},
 
-	{"MADD",    0xf200, 0xfeff, nop, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}},},
-	{"MSUB",    0xf600, 0xfeff, nop, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}},},
-	{"MADDX",   0xe000, 0xfcff, nop, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}},},
-	{"MSUBX",   0xe400, 0xfcff, nop, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}},},
-	{"MADDC",   0xe800, 0xfcff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}},},
-	{"MSUBC",   0xec00, 0xfcff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}},},
+	{"MADD",    0xf200, 0xfeff, DSPInterpreter::madd, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}},},
+	{"MSUB",    0xf600, 0xfeff, nop , nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}},},
+	{"MADDX",   0xe000, 0xfcff, DSPInterpreter::maddx, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}},},
+	{"MSUBX",   0xe400, 0xfcff, DSPInterpreter::msubx, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}},},
+	{"MADDC",   0xe800, 0xfcff, DSPInterpreter::maddc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}},},
+	{"MSUBC",   0xec00, 0xfcff, DSPInterpreter::msubc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}},},
 
 	// assemble CW
 	{"CW",      0x0000, 0xffff, nop, nop, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}},},
@@ -238,10 +240,10 @@ const u32 opcodes_ext_size = sizeof(opcodes_ext) / sizeof(DSPOPCTemplate);
 dspInstFunc opTable[OPTABLE_SIZE];
 
 void InitInstructionTable() {
-	for(int i = 0; i < OPTABLE_SIZE; i++)
+	for(u32 i = 0; i < OPTABLE_SIZE; i++)
 		opTable[i] = DSPInterpreter::unknown;
 
-	for(int i = 0; i < opcodes_size; i++)
+	for(u32 i = 0; i < opcodes_size; i++)
 		opTable[opcodes[i].opcode] = opcodes[i].interpFunc;
 }