ROM dissasm "refresh" + RE + small fixes

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4938 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Marko Pusljar 2010-01-24 00:31:20 +00:00
parent 1f37bb2177
commit fbdf721e0e
11 changed files with 2434 additions and 325 deletions

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@ -126,6 +126,7 @@ void lsrn(const UDSPInstruction& opc);
void asrn(const UDSPInstruction& opc); void asrn(const UDSPInstruction& opc);
void dar(const UDSPInstruction& opc); void dar(const UDSPInstruction& opc);
void iar(const UDSPInstruction& opc); void iar(const UDSPInstruction& opc);
void xar(const UDSPInstruction& opc);
void sbclr(const UDSPInstruction& opc); void sbclr(const UDSPInstruction& opc);
void sbset(const UDSPInstruction& opc); void sbset(const UDSPInstruction& opc);
void mov(const UDSPInstruction& opc); void mov(const UDSPInstruction& opc);

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@ -41,6 +41,7 @@ const DSPOPCTemplate opcodes[] =
{"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false}, {"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false},
{"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false}, {"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false},
{"XAR", 0x000c, 0xfffc, DSPInterpreter::xar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false},
{"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false}, {"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false},

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@ -129,6 +129,16 @@ void iar(const UDSPInstruction& opc)
g_dsp.r[opc.hex & 0x3] = dsp_increment_addr_reg(opc.hex & 0x3); g_dsp.r[opc.hex & 0x3] = dsp_increment_addr_reg(opc.hex & 0x3);
} }
// XAR $arD ?
// 0000 0000 0000 11dd
// $arD result somehow depends on $wrD
// unknown atm
// used in IPL ucode
void xar(const UDSPInstruction& opc)
{
// u8 dreg = opc.hex & 0x3;
}
// SBCLR #I // SBCLR #I
// 0001 0011 0000 0iii // 0001 0011 0000 0iii
// bit of status register $sr. Bit number is calculated by adding 6 to // bit of status register $sr. Bit number is calculated by adding 6 to

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@ -404,7 +404,11 @@ void CUCode_AX::HandleMail(u32 _uMail)
{ {
m_rMailHandler.PushMail(0xDCD10001); m_rMailHandler.PushMail(0xDCD10001);
} }
else if ((_uMail & 0xFFFF0000) == 0xCDD10000) // Action 1/2/3 else if (_uMail == 0xCDD10001) // Action 1 - new ucode upload
{
NOTICE_LOG(DSPHLE,"Game wanted to upload new ucode!");
}
else if ((_uMail & 0xFFFF0000) == 0xCDD10000) // Action 2/3
{ {
} }
else else

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@ -73,7 +73,11 @@ void CUCode_AXWii::HandleMail(u32 _uMail)
{ {
m_rMailHandler.PushMail(0xDCD10001); m_rMailHandler.PushMail(0xDCD10001);
} }
else if ((_uMail & 0xFFFF0000) == 0xCDD10000) // Action 1/2/3 else if (_uMail == 0xCDD10001) // Action 1 - new ucode upload
{
NOTICE_LOG(DSPHLE,"Game wanted to upload new ucode!");
}
else if ((_uMail & 0xFFFF0000) == 0xCDD10000) // Action 2/3
{ {
} }
else else

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@ -36,7 +36,7 @@ private:
u32 m_RAMAddress; u32 m_RAMAddress;
u32 m_Length; u32 m_Length;
u32 m_IMEMAddress; u32 m_IMEMAddress;
u32 m_Unk; u32 m_DMEMLength;
u32 m_StartPC; u32 m_StartPC;
}; };

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@ -68,7 +68,10 @@ void CUCode_Rom::HandleMail(u32 _uMail)
break; break;
case 0x80F3B002: case 0x80F3B002:
m_CurrentUCode.m_Unk = _uMail; m_CurrentUCode.m_DMEMLength = _uMail;
if (_uMail) {
NOTICE_LOG(DSPHLE,"Game wanted to DMA sth to DSP DRAM.");
}
break; break;
case 0x80F3D001: case 0x80F3D001:
@ -78,6 +81,9 @@ void CUCode_Rom::HandleMail(u32 _uMail)
return; // Important! BootUCode indirectly does "delete this;". Must exit immediately. return; // Important! BootUCode indirectly does "delete this;". Must exit immediately.
} }
break; break;
default:
break;
} }
// THE GODDAMN OVERWRITE WAS HERE. Without the return above, since BootUCode may delete "this", well ... // THE GODDAMN OVERWRITE WAS HERE. Without the return above, since BootUCode may delete "this", well ...
@ -100,7 +106,7 @@ void CUCode_Rom::BootUCode()
DEBUG_LOG(DSPHLE, "CurrentUCode SOURCE Addr: 0x%08x", m_CurrentUCode.m_RAMAddress); DEBUG_LOG(DSPHLE, "CurrentUCode SOURCE Addr: 0x%08x", m_CurrentUCode.m_RAMAddress);
DEBUG_LOG(DSPHLE, "CurrentUCode Length: 0x%08x", m_CurrentUCode.m_Length); DEBUG_LOG(DSPHLE, "CurrentUCode Length: 0x%08x", m_CurrentUCode.m_Length);
DEBUG_LOG(DSPHLE, "CurrentUCode DEST Addr: 0x%08x", m_CurrentUCode.m_IMEMAddress); DEBUG_LOG(DSPHLE, "CurrentUCode DEST Addr: 0x%08x", m_CurrentUCode.m_IMEMAddress);
DEBUG_LOG(DSPHLE, "CurrentUCode ???: 0x%08x", m_CurrentUCode.m_Unk); DEBUG_LOG(DSPHLE, "CurrentUCode DMEM Length: 0x%08x", m_CurrentUCode.m_DMEMLength);
DEBUG_LOG(DSPHLE, "CurrentUCode init_vector: 0x%08x", m_CurrentUCode.m_StartPC); DEBUG_LOG(DSPHLE, "CurrentUCode init_vector: 0x%08x", m_CurrentUCode.m_StartPC);
DEBUG_LOG(DSPHLE, "CurrentUCode CRC: 0x%08x", crc); DEBUG_LOG(DSPHLE, "CurrentUCode CRC: 0x%08x", crc);
DEBUG_LOG(DSPHLE, "BootTask - done"); DEBUG_LOG(DSPHLE, "BootTask - done");

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@ -35,7 +35,7 @@ private:
u32 m_RAMAddress; u32 m_RAMAddress;
u32 m_Length; u32 m_Length;
u32 m_IMEMAddress; u32 m_IMEMAddress;
u32 m_Unk; u32 m_DMEMLength;
u32 m_StartPC; u32 m_StartPC;
}; };

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@ -3224,15 +3224,15 @@ void 0f92_Int7_Handler() {
} }
// action jump table // action jump table
0f97 0fa9 lris $AC1.M, #0xa9 // Action 0 - restart 0f97 0fa9 // Action 0 - restart
0f98 0fac lris $AC1.M, #0xac // Action 1 - wait for 10 mails and dump memory? 0f98 0fac // Action 1 - dump DRAM and jump into iROM where new IRAM and DRAM can be uploaded
0f99 0fe4 lris $AC1.M, #0xe4 // Action 2 - soft reset 0f99 0fe4 // Action 2 - soft reset
0f9a 0fe7 lris $AC1.M, #0xe7 // Action 3 - jump back to main loop 0f9a 0fe7 // Action 3 - jump back to main loop
// called at AXList end; wait for a last mail and take an action // called at AXList end; wait for a last mail and take an action
// Note: the same thing can be found in Zelda ucode. It's called after DsyncFrame. // Note: the same thing can be found in Zelda ucode. It's called after DsyncFrame.
// Probably debugging stuff. // Probably debugging stuff.
{
0f9b 8e00 set16 0f9b 8e00 set16
0f9c 8100 clr $ACC0 0f9c 8100 clr $ACC0
0f9d 8900 clr $ACC1 0f9d 8900 clr $ACC1
@ -3245,10 +3245,16 @@ void 0f92_Int7_Handler() {
0fa6 1c7f mrr $AR3, $AC1.M 0fa6 1c7f mrr $AR3, $AC1.M
0fa7 176f jmpr $AR3 // take the action! 0fa7 176f jmpr $AR3 // take the action!
0fa8 0021 halt 0fa8 0021 halt
}
//ACTION 0 (0xCDD10000)
{
0fa9 029f 0037 jmp 0037_Unk_Restart() 0fa9 029f 0037 jmp 0037_Unk_Restart()
0fab 0021 halt 0fab 0021 halt
}
//ACTION 1 (0xCDD10001)
{
0fac 8100 clr $ACC0 0fac 8100 clr $ACC0
0fad 8900 clr $ACC1 0fad 8900 clr $ACC1
0fae 02bf 0fea call 0x0fea 0fae 02bf 0fea call 0x0fea
@ -3259,12 +3265,13 @@ void 0f92_Int7_Handler() {
0fb6 27ff lrs $AC1.M, @CMBL 0fb6 27ff lrs $AC1.M, @CMBL
0fb7 2ece srs @DSMAH, $AC0.M 0fb7 2ece srs @DSMAH, $AC0.M
0fb8 2ccf srs @DSMAL, $AC0.L 0fb8 2ccf srs @DSMAL, $AC0.L
0fb9 16c9 0001 si @DSCR, #0x0001 0fb9 16c9 0001 si @DSCR, #0x0001 // DMEM->CPU
0fbb 2fcd srs @DSPA, $AC1.M 0fbb 2fcd srs @DSPA, $AC1.M
0fbc 2dcb srs @DSBL, $AC1.L 0fbc 2dcb srs @DSBL, $AC1.L
0fbd 8100 clr $ACC0 0fbd 8100 clr $ACC0
0fbe 8900 clr $ACC1 0fbe 8900 clr $ACC1
0fbf 02bf 0fea call 0x0fea 0fbf 02bf 0fea call 0x0fea
//prepare addr-s/length/dsp-PC for new IRAM/DRAM
0fc1 24ff lrs $AC0.L, @CMBL 0fc1 24ff lrs $AC0.L, @CMBL
0fc2 1c9e mrr $IX0, $AC0.M 0fc2 1c9e mrr $IX0, $AC0.M
0fc3 1cbc mrr $IX1, $AC0.L 0fc3 1cbc mrr $IX1, $AC0.L
@ -3286,25 +3293,39 @@ void 0f92_Int7_Handler() {
0fd8 21ff lrs $AX1.L, @CMBL 0fd8 21ff lrs $AX1.L, @CMBL
0fd9 02bf 0fea call 0x0fea 0fd9 02bf 0fea call 0x0fea
0fdb 23ff lrs $AX1.H, @CMBL 0fdb 23ff lrs $AX1.H, @CMBL
//
0fdc 26c9 lrs $AC0.M, @DSCR 0fdc 26c9 lrs $AC0.M, @DSCR
0fdd 02a0 0004 andf $AC0.M, #0x0004 0fdd 02a0 0004 andf $AC0.M, #0x0004
0fdf 029c 0fdc jlnz 0x0fdc 0fdf 029c 0fdc jlnz 0x0fdc
0fe1 029f 80b5 jmp 0x80b5 0fe1 029f 80b5 jmp 0x80b5 // 80b5_BootUcode()
0fe3 0021 halt 0fe3 0021 halt
}
//ACTION 2 (0xCDD10002)
{
0fe4 029f 8000 jmp 0x8000 0fe4 029f 8000 jmp 0x8000
0fe6 0021 halt 0fe6 0021 halt
}
//ACTION 3 (0xCDD10003)
{
0fe7 029f 004c jmp 0x004c 0fe7 029f 004c jmp 0x004c
0fe9 0021 halt 0fe9 0021 halt
}
{
0fea 26fe lrs $AC0.M, @CMBH 0fea 26fe lrs $AC0.M, @CMBH
0feb 02c0 8000 andcf $AC0.M, #0x8000 0feb 02c0 8000 andcf $AC0.M, #0x8000
0fed 029c 0fea jlnz 0x0fea 0fed 029c 0fea jlnz 0x0fea
0fef 02df ret 0fef 02df ret
}
{
0ff0 27fe lrs $AC1.M, @CMBH 0ff0 27fe lrs $AC1.M, @CMBH
0ff1 03c0 8000 andcf $AC1.M, #0x8000 0ff1 03c0 8000 andcf $AC1.M, #0x8000
0ff3 029c 0ff0 jlnz 0x0ff0 0ff3 029c 0ff0 jlnz 0x0ff0
0ff5 02df ret 0ff5 02df ret
}
0ff6 0000 nop 0ff6 0000 nop
0ff7 0000 nop 0ff7 0000 nop

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff