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Core/DSPCore: Reorganize register layout for accessing accumulators
(acc and ax) and product register with one read/write. Gives a minuscule speedup of not more than 4%. In exchange, breaks all your out-of-tree changes to dsp. Tests are not building again, yet. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6680 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
@ -28,128 +28,128 @@ namespace DSPInterpreter {
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void Update_SR_Register64(s64 _Value, bool carry, bool overflow)
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{
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g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK;
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g_dsp._r.sr &= ~SR_CMP_MASK;
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// 0x01
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if (carry)
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{
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g_dsp.r[DSP_REG_SR] |= SR_CARRY;
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g_dsp._r.sr |= SR_CARRY;
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}
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// 0x02 and 0x80
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if (overflow)
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{
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g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW;
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g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW_STICKY;
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g_dsp._r.sr |= SR_OVERFLOW;
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g_dsp._r.sr |= SR_OVERFLOW_STICKY;
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}
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// 0x04
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if (_Value == 0)
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{
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g_dsp.r[DSP_REG_SR] |= SR_ARITH_ZERO;
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g_dsp._r.sr |= SR_ARITH_ZERO;
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}
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// 0x08
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if (_Value < 0)
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{
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g_dsp.r[DSP_REG_SR] |= SR_SIGN;
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g_dsp._r.sr |= SR_SIGN;
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}
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// 0x10
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if (_Value != (s32)_Value)
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{
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g_dsp.r[DSP_REG_SR] |= SR_OVER_S32;
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g_dsp._r.sr |= SR_OVER_S32;
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}
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// 0x20 - Checks if top bits of m are equal
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if (((_Value & 0xc0000000) == 0) || ((_Value & 0xc0000000) == 0xc0000000))
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{
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g_dsp.r[DSP_REG_SR] |= SR_TOP2BITS;
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g_dsp._r.sr |= SR_TOP2BITS;
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}
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}
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void Update_SR_Register16(s16 _Value, bool carry, bool overflow, bool overS32)
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{
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g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK;
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g_dsp._r.sr &= ~SR_CMP_MASK;
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// 0x01
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if (carry)
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{
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g_dsp.r[DSP_REG_SR] |= SR_CARRY;
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g_dsp._r.sr |= SR_CARRY;
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}
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// 0x02 and 0x80
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if (overflow)
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{
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g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW;
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g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW_STICKY;
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g_dsp._r.sr |= SR_OVERFLOW;
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g_dsp._r.sr |= SR_OVERFLOW_STICKY;
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}
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// 0x04
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if (_Value == 0)
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{
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g_dsp.r[DSP_REG_SR] |= SR_ARITH_ZERO;
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g_dsp._r.sr |= SR_ARITH_ZERO;
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}
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// 0x08
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if (_Value < 0)
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{
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g_dsp.r[DSP_REG_SR] |= SR_SIGN;
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g_dsp._r.sr |= SR_SIGN;
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}
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// 0x10
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if (overS32)
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{
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g_dsp.r[DSP_REG_SR] |= SR_OVER_S32;
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g_dsp._r.sr |= SR_OVER_S32;
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}
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// 0x20 - Checks if top bits of m are equal
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if ((((u16)_Value >> 14) == 0) || (((u16)_Value >> 14) == 3))
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{
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g_dsp.r[DSP_REG_SR] |= SR_TOP2BITS;
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g_dsp._r.sr |= SR_TOP2BITS;
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}
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}
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void Update_SR_LZ(bool value)
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{
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if (value == true)
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g_dsp.r[DSP_REG_SR] |= SR_LOGIC_ZERO;
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g_dsp._r.sr |= SR_LOGIC_ZERO;
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else
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g_dsp.r[DSP_REG_SR] &= ~SR_LOGIC_ZERO;
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g_dsp._r.sr &= ~SR_LOGIC_ZERO;
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}
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inline int GetMultiplyModifier()
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{
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return (g_dsp.r[DSP_REG_SR] & SR_MUL_MODIFY)?1:2;
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return (g_dsp._r.sr & SR_MUL_MODIFY)?1:2;
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}
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inline bool isCarry() {
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return (g_dsp.r[DSP_REG_SR] & SR_CARRY) ? true : false;
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return (g_dsp._r.sr & SR_CARRY) ? true : false;
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}
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inline bool isOverflow() {
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return (g_dsp.r[DSP_REG_SR] & SR_OVERFLOW) ? true : false;
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return (g_dsp._r.sr & SR_OVERFLOW) ? true : false;
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}
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inline bool isOverS32() {
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return (g_dsp.r[DSP_REG_SR] & SR_OVER_S32) ? true : false;
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return (g_dsp._r.sr & SR_OVER_S32) ? true : false;
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}
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inline bool isLess() {
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return (!(g_dsp.r[DSP_REG_SR] & SR_OVERFLOW) != !(g_dsp.r[DSP_REG_SR] & SR_SIGN));
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return (!(g_dsp._r.sr & SR_OVERFLOW) != !(g_dsp._r.sr & SR_SIGN));
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}
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inline bool isZero() {
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return (g_dsp.r[DSP_REG_SR] & SR_ARITH_ZERO) ? true : false;
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return (g_dsp._r.sr & SR_ARITH_ZERO) ? true : false;
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}
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inline bool isLogicZero() {
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return (g_dsp.r[DSP_REG_SR] & SR_LOGIC_ZERO) ? true : false;
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return (g_dsp._r.sr & SR_LOGIC_ZERO) ? true : false;
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}
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inline bool isConditionA() {
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return (((g_dsp.r[DSP_REG_SR] & SR_OVER_S32) || (g_dsp.r[DSP_REG_SR] & SR_TOP2BITS)) && !(g_dsp.r[DSP_REG_SR] & SR_ARITH_ZERO)) ? true : false;
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return (((g_dsp._r.sr & SR_OVER_S32) || (g_dsp._r.sr & SR_TOP2BITS)) && !(g_dsp._r.sr & SR_ARITH_ZERO)) ? true : false;
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}
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//see DSPCore.h for flags
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