Core/DSPCore: Reorganize register layout for accessing accumulators

(acc and ax) and product register with one read/write.

Gives a minuscule speedup of not more than 4%. In exchange, breaks all
your out-of-tree changes to dsp. Tests are not building again, yet.


git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6680 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
pierre
2010-12-29 02:12:06 +00:00
parent 0059b0f44f
commit fc1db5eaa0
23 changed files with 1224 additions and 728 deletions

View File

@ -28,128 +28,128 @@ namespace DSPInterpreter {
void Update_SR_Register64(s64 _Value, bool carry, bool overflow)
{
g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK;
g_dsp._r.sr &= ~SR_CMP_MASK;
// 0x01
if (carry)
{
g_dsp.r[DSP_REG_SR] |= SR_CARRY;
g_dsp._r.sr |= SR_CARRY;
}
// 0x02 and 0x80
if (overflow)
{
g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW;
g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW_STICKY;
g_dsp._r.sr |= SR_OVERFLOW;
g_dsp._r.sr |= SR_OVERFLOW_STICKY;
}
// 0x04
if (_Value == 0)
{
g_dsp.r[DSP_REG_SR] |= SR_ARITH_ZERO;
g_dsp._r.sr |= SR_ARITH_ZERO;
}
// 0x08
if (_Value < 0)
{
g_dsp.r[DSP_REG_SR] |= SR_SIGN;
g_dsp._r.sr |= SR_SIGN;
}
// 0x10
if (_Value != (s32)_Value)
{
g_dsp.r[DSP_REG_SR] |= SR_OVER_S32;
g_dsp._r.sr |= SR_OVER_S32;
}
// 0x20 - Checks if top bits of m are equal
if (((_Value & 0xc0000000) == 0) || ((_Value & 0xc0000000) == 0xc0000000))
{
g_dsp.r[DSP_REG_SR] |= SR_TOP2BITS;
g_dsp._r.sr |= SR_TOP2BITS;
}
}
void Update_SR_Register16(s16 _Value, bool carry, bool overflow, bool overS32)
{
g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK;
g_dsp._r.sr &= ~SR_CMP_MASK;
// 0x01
if (carry)
{
g_dsp.r[DSP_REG_SR] |= SR_CARRY;
g_dsp._r.sr |= SR_CARRY;
}
// 0x02 and 0x80
if (overflow)
{
g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW;
g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW_STICKY;
g_dsp._r.sr |= SR_OVERFLOW;
g_dsp._r.sr |= SR_OVERFLOW_STICKY;
}
// 0x04
if (_Value == 0)
{
g_dsp.r[DSP_REG_SR] |= SR_ARITH_ZERO;
g_dsp._r.sr |= SR_ARITH_ZERO;
}
// 0x08
if (_Value < 0)
{
g_dsp.r[DSP_REG_SR] |= SR_SIGN;
g_dsp._r.sr |= SR_SIGN;
}
// 0x10
if (overS32)
{
g_dsp.r[DSP_REG_SR] |= SR_OVER_S32;
g_dsp._r.sr |= SR_OVER_S32;
}
// 0x20 - Checks if top bits of m are equal
if ((((u16)_Value >> 14) == 0) || (((u16)_Value >> 14) == 3))
{
g_dsp.r[DSP_REG_SR] |= SR_TOP2BITS;
g_dsp._r.sr |= SR_TOP2BITS;
}
}
void Update_SR_LZ(bool value)
{
if (value == true)
g_dsp.r[DSP_REG_SR] |= SR_LOGIC_ZERO;
g_dsp._r.sr |= SR_LOGIC_ZERO;
else
g_dsp.r[DSP_REG_SR] &= ~SR_LOGIC_ZERO;
g_dsp._r.sr &= ~SR_LOGIC_ZERO;
}
inline int GetMultiplyModifier()
{
return (g_dsp.r[DSP_REG_SR] & SR_MUL_MODIFY)?1:2;
return (g_dsp._r.sr & SR_MUL_MODIFY)?1:2;
}
inline bool isCarry() {
return (g_dsp.r[DSP_REG_SR] & SR_CARRY) ? true : false;
return (g_dsp._r.sr & SR_CARRY) ? true : false;
}
inline bool isOverflow() {
return (g_dsp.r[DSP_REG_SR] & SR_OVERFLOW) ? true : false;
return (g_dsp._r.sr & SR_OVERFLOW) ? true : false;
}
inline bool isOverS32() {
return (g_dsp.r[DSP_REG_SR] & SR_OVER_S32) ? true : false;
return (g_dsp._r.sr & SR_OVER_S32) ? true : false;
}
inline bool isLess() {
return (!(g_dsp.r[DSP_REG_SR] & SR_OVERFLOW) != !(g_dsp.r[DSP_REG_SR] & SR_SIGN));
return (!(g_dsp._r.sr & SR_OVERFLOW) != !(g_dsp._r.sr & SR_SIGN));
}
inline bool isZero() {
return (g_dsp.r[DSP_REG_SR] & SR_ARITH_ZERO) ? true : false;
return (g_dsp._r.sr & SR_ARITH_ZERO) ? true : false;
}
inline bool isLogicZero() {
return (g_dsp.r[DSP_REG_SR] & SR_LOGIC_ZERO) ? true : false;
return (g_dsp._r.sr & SR_LOGIC_ZERO) ? true : false;
}
inline bool isConditionA() {
return (((g_dsp.r[DSP_REG_SR] & SR_OVER_S32) || (g_dsp.r[DSP_REG_SR] & SR_TOP2BITS)) && !(g_dsp.r[DSP_REG_SR] & SR_ARITH_ZERO)) ? true : false;
return (((g_dsp._r.sr & SR_OVER_S32) || (g_dsp._r.sr & SR_TOP2BITS)) && !(g_dsp._r.sr & SR_ARITH_ZERO)) ? true : false;
}
//see DSPCore.h for flags