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Core/DSPCore: Reorganize register layout for accessing accumulators

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(acc and ax) and product register with one read/write.

Gives a minuscule speedup of not more than 4%. In exchange, breaks all
your out-of-tree changes to dsp. Tests are not building again, yet.


git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6680 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
pierre
2010-12-29 02:12:06 +00:00
parent 0059b0f44f
commit fc1db5eaa0
23 changed files with 1224 additions and 728 deletions
Download Patch File Download Diff File Expand all files Collapse all files

217
Source/Core/DSPCore/Src/DSPIntExtOps.cpp
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@ -70,7 +70,7 @@ void ir(const UDSPInstruction opc) {
void nr(const UDSPInstruction opc) {
u8 reg = opc & 0x3;
writeToBackLog(0, reg, dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]));
writeToBackLog(0, reg, dsp_increase_addr_reg(reg, (s16)g_dsp._r.ix[reg]));
}
// MV $axD.D, $acS.S
@ -81,7 +81,16 @@ void mv(const UDSPInstruction opc)
u8 sreg = (opc & 0x3) + DSP_REG_ACL0;
u8 dreg = ((opc >> 2) & 0x3);
writeToBackLog(0, dreg + DSP_REG_AXL0, g_dsp.r[sreg]);
switch(sreg) {
case DSP_REG_ACL0:
case DSP_REG_ACL1:
writeToBackLog(0, dreg + DSP_REG_AXL0, g_dsp._r.ac[sreg-DSP_REG_ACL0].l);
break;
case DSP_REG_ACM0:
case DSP_REG_ACM1:
writeToBackLog(0, dreg + DSP_REG_AXL0, g_dsp._r.ac[sreg-DSP_REG_ACM0].m);
break;
}
}
// S @$arD, $acS.S
@ -93,7 +102,16 @@ void s(const UDSPInstruction opc)
u8 dreg = opc & 0x3;
u8 sreg = ((opc >> 3) & 0x3) + DSP_REG_ACL0;
dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
switch(sreg) {
case DSP_REG_ACL0:
case DSP_REG_ACL1:
dsp_dmem_write(g_dsp._r.ar[dreg], g_dsp._r.ac[sreg-DSP_REG_ACL0].l);
break;
case DSP_REG_ACM0:
case DSP_REG_ACM1:
dsp_dmem_write(g_dsp._r.ar[dreg], g_dsp._r.ac[sreg-DSP_REG_ACM0].m);
break;
}
writeToBackLog(0, dreg, dsp_increment_addr_reg(dreg));
}
@ -106,8 +124,17 @@ void sn(const UDSPInstruction opc)
u8 dreg = opc & 0x3;
u8 sreg = ((opc >> 3) & 0x3) + DSP_REG_ACL0;
dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
writeToBackLog(0, dreg, dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]));
switch(sreg) {
case DSP_REG_ACL0:
case DSP_REG_ACL1:
dsp_dmem_write(g_dsp._r.ar[dreg], g_dsp._r.ac[sreg-DSP_REG_ACL0].l);
break;
case DSP_REG_ACM0:
case DSP_REG_ACM1:
dsp_dmem_write(g_dsp._r.ar[dreg], g_dsp._r.ac[sreg-DSP_REG_ACM0].m);
break;
}
writeToBackLog(0, dreg, dsp_increase_addr_reg(dreg, (s16)g_dsp._r.ix[dreg]));
}
// L $axD.D, @$arS
@ -119,9 +146,9 @@ void l(const UDSPInstruction opc)
u8 sreg = opc & 0x3;
u8 dreg = ((opc >> 3) & 0x7) + DSP_REG_AXL0;
if ((dreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT))
if ((dreg >= DSP_REG_ACM0) && (g_dsp._r.sr & SR_40_MODE_BIT))
{
u16 val = dsp_dmem_read(g_dsp.r[sreg]);
u16 val = dsp_dmem_read(g_dsp._r.ar[sreg]);
writeToBackLog(0, dreg - DSP_REG_ACM0 + DSP_REG_ACH0, (val & 0x8000) ? 0xFFFF : 0x0000);
writeToBackLog(1, dreg, val);
writeToBackLog(2, dreg - DSP_REG_ACM0 + DSP_REG_ACL0, 0);
@ -129,7 +156,7 @@ void l(const UDSPInstruction opc)
}
else
{
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[sreg]));
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp._r.ar[sreg]));
writeToBackLog(1, sreg, dsp_increment_addr_reg(sreg));
}
}
@ -143,34 +170,34 @@ void ln(const UDSPInstruction opc)
u8 sreg = opc & 0x3;
u8 dreg = ((opc >> 3) & 0x7) + DSP_REG_AXL0;
if ((dreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT))
if ((dreg >= DSP_REG_ACM0) && (g_dsp._r.sr & SR_40_MODE_BIT))
{
u16 val = dsp_dmem_read(g_dsp.r[sreg]);
u16 val = dsp_dmem_read(g_dsp._r.ar[sreg]);
writeToBackLog(0, dreg - DSP_REG_ACM0 + DSP_REG_ACH0, (val & 0x8000) ? 0xFFFF : 0x0000);
writeToBackLog(1, dreg, val);
writeToBackLog(2, dreg - DSP_REG_ACM0 + DSP_REG_ACL0, 0);
writeToBackLog(3, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
writeToBackLog(3, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp._r.ix[sreg]));
}
else
{
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[sreg]));
writeToBackLog(1, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp._r.ar[sreg]));
writeToBackLog(1, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp._r.ix[sreg]));
}
}
// LS $axD.D, $acS.m
// LS $axD.D, $acS.m108
// xxxx xxxx 10dd 000s
// Load register $axD.D with value from memory pointed by register
// $ar0. Store value from register $acS.m to memory location pointed by
// register $ar3. Increment both $ar0 and $ar3.
void ls(const UDSPInstruction opc)
{
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
u8 sreg = opc & 0x1;
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
dsp_dmem_write(g_dsp.r[DSP_REG_AR3], g_dsp.r[sreg]);
dsp_dmem_write(g_dsp._r.ar[3], g_dsp._r.ac[sreg].m);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR0]));
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp._r.ar[0]));
writeToBackLog(1, DSP_REG_AR3, dsp_increment_addr_reg(DSP_REG_AR3));
writeToBackLog(2, DSP_REG_AR0, dsp_increment_addr_reg(DSP_REG_AR0));
}
@ -184,14 +211,14 @@ void ls(const UDSPInstruction opc)
// register $ar0 and increment $ar3.
void lsn(const UDSPInstruction opc)
{
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
u8 sreg = opc & 0x1;
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
dsp_dmem_write(g_dsp.r[DSP_REG_AR3], g_dsp.r[sreg]);
dsp_dmem_write(g_dsp._r.ar[3], g_dsp._r.ac[sreg].m);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR0]));
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp._r.ar[0]));
writeToBackLog(1, DSP_REG_AR3, dsp_increment_addr_reg(DSP_REG_AR3));
writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp.r[DSP_REG_IX0]));
writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp._r.ix[0]));
}
// LSM $axD.D, $acS.m
@ -202,13 +229,13 @@ void lsn(const UDSPInstruction opc)
// register $ar3 and increment $ar0.
void lsm(const UDSPInstruction opc)
{
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
u8 sreg = opc & 0x1;
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
dsp_dmem_write(g_dsp.r[DSP_REG_AR3], g_dsp.r[sreg]);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR0]));
writeToBackLog(1, DSP_REG_AR3, dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX3]));
dsp_dmem_write(g_dsp._r.ar[3], g_dsp._r.ac[sreg].m);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp._r.ar[0]));
writeToBackLog(1, DSP_REG_AR3, dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp._r.ix[3]));
writeToBackLog(2, DSP_REG_AR0, dsp_increment_addr_reg(DSP_REG_AR0));
}
@ -221,14 +248,14 @@ void lsm(const UDSPInstruction opc)
// register $ar3.
void lsnm(const UDSPInstruction opc)
{
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
u8 sreg = opc & 0x1;
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
dsp_dmem_write(g_dsp.r[DSP_REG_AR3], g_dsp.r[sreg]);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR0]));
writeToBackLog(1, DSP_REG_AR3, dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX3]));
writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp.r[DSP_REG_IX0]));
dsp_dmem_write(g_dsp._r.ar[3], g_dsp._r.ac[sreg].m);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp._r.ar[0]));
writeToBackLog(1, DSP_REG_AR3, dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp._r.ix[3]));
writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp._r.ix[0]));
}
// SL $acS.m, $axD.D
@ -238,12 +265,12 @@ void lsnm(const UDSPInstruction opc)
// $ar3. Increment both $ar0 and $ar3.
void sl(const UDSPInstruction opc)
{
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
u8 sreg = opc & 0x1;
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[sreg]);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
dsp_dmem_write(g_dsp._r.ar[0], g_dsp._r.ac[sreg].m);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp._r.ar[3]));
writeToBackLog(1, DSP_REG_AR3, dsp_increment_addr_reg(DSP_REG_AR3));
writeToBackLog(2, DSP_REG_AR0, dsp_increment_addr_reg(DSP_REG_AR0));
}
@ -256,14 +283,14 @@ void sl(const UDSPInstruction opc)
// and increment $ar3.
void sln(const UDSPInstruction opc)
{
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
u8 sreg = opc & 0x1;
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[sreg]);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
dsp_dmem_write(g_dsp._r.ar[0], g_dsp._r.ac[sreg].m);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp._r.ar[3]));
writeToBackLog(1, DSP_REG_AR3, dsp_increment_addr_reg(DSP_REG_AR3));
writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp.r[DSP_REG_IX0]));
writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp._r.ix[0]));
}
// SLM $acS.m, $axD.D
@ -274,13 +301,13 @@ void sln(const UDSPInstruction opc)
// and increment $ar0.
void slm(const UDSPInstruction opc)
{
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
u8 sreg = opc & 0x1;
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[sreg]);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
writeToBackLog(1, DSP_REG_AR3, dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX3]));
dsp_dmem_write(g_dsp._r.ar[0], g_dsp._r.ac[sreg].m);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp._r.ar[3]));
writeToBackLog(1, DSP_REG_AR3, dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp._r.ix[3]));
writeToBackLog(2, DSP_REG_AR0, dsp_increment_addr_reg(DSP_REG_AR0));
}
@ -292,14 +319,14 @@ void slm(const UDSPInstruction opc)
// and add corresponding indexing register $ix3 to addressing register $ar3.
void slnm(const UDSPInstruction opc)
{
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
u8 sreg = opc & 0x1;
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[sreg]);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
writeToBackLog(1, DSP_REG_AR3, dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX3]));
writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp.r[DSP_REG_IX0]));
dsp_dmem_write(g_dsp._r.ar[0], g_dsp._r.ac[sreg].m);
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp._r.ar[3]));
writeToBackLog(1, DSP_REG_AR3, dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp._r.ix[3]));
writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp._r.ix[0]));
}
// LD $ax0.d, $ax1.r, @$arS
@ -318,21 +345,21 @@ void ld(const UDSPInstruction opc)
u8 sreg = opc & 0x3;
if (sreg != DSP_REG_AR3) {
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg]));
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp._r.ar[sreg]));
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[sreg]));
if (IsSameMemArea(g_dsp._r.ar[sreg], g_dsp._r.ar[3]))
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp._r.ar[sreg]));
else
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp._r.ar[3]));
writeToBackLog(2, sreg, dsp_increment_addr_reg(sreg));
} else {
writeToBackLog(0, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[dreg]));
writeToBackLog(0, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp._r.ar[dreg]));
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[dreg]));
if (IsSameMemArea(g_dsp._r.ar[dreg], g_dsp._r.ar[3]))
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp._r.ar[dreg]));
else
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp._r.ar[3]));
writeToBackLog(2, dreg, dsp_increment_addr_reg(dreg));
}
@ -347,27 +374,27 @@ void ldn(const UDSPInstruction opc)
u8 dreg = (opc >> 5) & 0x1;
u8 rreg = (opc >> 4) & 0x1;
u8 sreg = opc & 0x3;
if (sreg != DSP_REG_AR3) {
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg]));
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp._r.ar[sreg]));
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[sreg]));
if (IsSameMemArea(g_dsp._r.ar[sreg], g_dsp._r.ar[3]))
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp._r.ar[sreg]));
else
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp._r.ar[3]));
writeToBackLog(2, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
writeToBackLog(2, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp._r.ix[sreg]));
} else {
writeToBackLog(0, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[dreg]));
writeToBackLog(0, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp._r.ar[dreg]));
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[dreg]));
if (IsSameMemArea(g_dsp._r.ar[dreg], g_dsp._r.ar[3]))
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp._r.ar[dreg]));
else
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp._r.ar[3]));
writeToBackLog(2, dreg, dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]));
writeToBackLog(2, dreg, dsp_increase_addr_reg(dreg, (s16)g_dsp._r.ix[dreg]));
}
writeToBackLog(3, DSP_REG_AR3, dsp_increment_addr_reg(DSP_REG_AR3));
}
@ -380,27 +407,27 @@ void ldm(const UDSPInstruction opc)
u8 sreg = opc & 0x3;
if (sreg != DSP_REG_AR3) {
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg]));
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp._r.ar[sreg]));
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[sreg]));
if (IsSameMemArea(g_dsp._r.ar[sreg], g_dsp._r.ar[3]))
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp._r.ar[sreg]));
else
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp._r.ar[3]));
writeToBackLog(2, sreg, dsp_increment_addr_reg(sreg));
} else {
writeToBackLog(0, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[dreg]));
writeToBackLog(0, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp._r.ar[dreg]));
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[dreg]));
if (IsSameMemArea(g_dsp._r.ar[dreg], g_dsp._r.ar[3]))
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp._r.ar[dreg]));
else
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp._r.ar[3]));
writeToBackLog(2, dreg, dsp_increment_addr_reg(dreg));
}
writeToBackLog(3, DSP_REG_AR3,
dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX3]));
dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp._r.ix[3]));
}
// LDNM $ax0.d, $ax1.r, @$arS
@ -412,27 +439,27 @@ void ldnm(const UDSPInstruction opc)
u8 sreg = opc & 0x3;
if (sreg != DSP_REG_AR3) {
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg]));
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp._r.ar[sreg]));
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[sreg]));
if (IsSameMemArea(g_dsp._r.ar[sreg], g_dsp._r.ar[3]))
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp._r.ar[sreg]));
else
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp._r.ar[3]));
writeToBackLog(2, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
writeToBackLog(2, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp._r.ix[sreg]));
} else {
writeToBackLog(0, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[dreg]));
writeToBackLog(0, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp._r.ar[dreg]));
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[dreg]));
if (IsSameMemArea(g_dsp._r.ar[dreg], g_dsp._r.ar[3]))
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp._r.ar[dreg]));
else
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp._r.ar[3]));
writeToBackLog(2, dreg, dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]));
writeToBackLog(2, dreg, dsp_increase_addr_reg(dreg, (s16)g_dsp._r.ix[dreg]));
}
writeToBackLog(3, DSP_REG_AR3,
dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX3]));
dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp._r.ix[3]));
}
@ -457,7 +484,7 @@ void applyWriteBackLog()
// always make sure to have an extra entry at the end w/ -1 to avoid
// infinitive loops
for (int i = 0; writeBackLogIdx[i] != -1; i++) {
dsp_op_write_reg(writeBackLogIdx[i], g_dsp.r[writeBackLogIdx[i]] | writeBackLog[i]);
dsp_op_write_reg(writeBackLogIdx[i], dsp_op_read_reg(writeBackLogIdx[i]) | writeBackLog[i]);
// Clear back log
writeBackLogIdx[i] = -1;
}
@ -468,7 +495,7 @@ void applyWriteBackLog()
// apply the ext command output, because if the main op didn't change the value
// then 0 | ext output = ext output and if it did then bitwise or is still the
// right thing to do
void zeroWriteBackLog()
void zeroWriteBackLog()
{
// always make sure to have an extra entry at the end w/ -1 to avoid
// infinitive loops