From fdc141e333d9d7d57ea056968c86afbc55bc6310 Mon Sep 17 00:00:00 2001
From: nakeee <nakeee@gmail.com>
Date: Thu, 20 Aug 2009 13:49:30 +0000
Subject: [PATCH] DSPLLE: Small fixes for zeroing flags

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4020 8ced0084-cf51-0410-be5f-012b33b47a6e
---
 Source/Core/DSPCore/Src/DspIntArithmetic.cpp | 25 ++++++++++++--------
 Source/Core/DSPCore/Src/DspIntLoadStore.cpp  |  2 +-
 2 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/Source/Core/DSPCore/Src/DspIntArithmetic.cpp b/Source/Core/DSPCore/Src/DspIntArithmetic.cpp
index c4c9018ddc..e2e4491f03 100644
--- a/Source/Core/DSPCore/Src/DspIntArithmetic.cpp
+++ b/Source/Core/DSPCore/Src/DspIntArithmetic.cpp
@@ -144,10 +144,11 @@ void xorr(const UDSPInstruction& opc)
 {
 	u8 sreg = (opc.hex >> 9) & 0x1;
 	u8 dreg = (opc.hex >> 8) & 0x1;
-
+	u16 axh = g_dsp.r[DSP_REG_AXH0 + sreg];
+	
 	zeroWriteBackLog();
 
-	g_dsp.r[DSP_REG_ACM0 + dreg] ^= g_dsp.r[DSP_REG_AXH0 + sreg];
+	g_dsp.r[DSP_REG_ACM0 + dreg] ^= axh;
 
 	s64 acc = dsp_get_long_acc(dreg);
 	Update_SR_Register64(acc);
@@ -161,10 +162,11 @@ void andr(const UDSPInstruction& opc)
 {
 	u8 sreg = (opc.hex >> 9) & 0x1;
 	u8 dreg = (opc.hex >> 8) & 0x1;
-
+	u16 axh = g_dsp.r[DSP_REG_AXH0 + sreg];
+	
 	zeroWriteBackLog();
 
-	g_dsp.r[DSP_REG_ACM0 + dreg] &= g_dsp.r[DSP_REG_AXH0 + sreg];
+	g_dsp.r[DSP_REG_ACM0 + dreg] &= axh;
 
 	s64 acc = dsp_get_long_acc(dreg);
 	Update_SR_Register64(acc);
@@ -178,10 +180,11 @@ void orr(const UDSPInstruction& opc)
 {
 	u8 sreg = (opc.hex >> 9) & 0x1;
 	u8 dreg = (opc.hex >> 8) & 0x1;
-
+	u16 axh = g_dsp.r[DSP_REG_AXH0 + sreg];
+	
 	zeroWriteBackLog();
 
-	g_dsp.r[DSP_REG_ACM0 + dreg] |= g_dsp.r[DSP_REG_AXH0 + sreg];
+	g_dsp.r[DSP_REG_ACM0 + dreg] |= axh;
 
 	s64 acc = dsp_get_long_acc(dreg);
 	Update_SR_Register64(acc);
@@ -195,10 +198,11 @@ void orr(const UDSPInstruction& opc)
 void andc(const UDSPInstruction& opc)
 {
 	u8 D = (opc.hex >> 8) & 0x1;
-
+	u16 accm = dsp_get_acc_m(1-D);
+	
 	zeroWriteBackLog();
 
-	g_dsp.r[DSP_REG_ACM0+D] &= dsp_get_acc_m(1-D);
+	g_dsp.r[DSP_REG_ACM0+D] &= accm;
 
 	Update_SR_Register16(dsp_get_acc_m(D));
 }
@@ -211,10 +215,11 @@ void andc(const UDSPInstruction& opc)
 void orc(const UDSPInstruction& opc)
 {
 	u8 D = (opc.hex >> 8) & 0x1;
-
+	u16 accm = dsp_get_acc_m(1-D);
+	
 	zeroWriteBackLog();
 
-	g_dsp.r[DSP_REG_ACM0+D] |= dsp_get_acc_m(1-D);
+	g_dsp.r[DSP_REG_ACM0+D] |= accm;
 
 	Update_SR_Register16(dsp_get_acc_m(D));
 }
diff --git a/Source/Core/DSPCore/Src/DspIntLoadStore.cpp b/Source/Core/DSPCore/Src/DspIntLoadStore.cpp
index 975ef3bccd..7400dfdb08 100644
--- a/Source/Core/DSPCore/Src/DspIntLoadStore.cpp
+++ b/Source/Core/DSPCore/Src/DspIntLoadStore.cpp
@@ -176,7 +176,7 @@ void srrd(const UDSPInstruction& opc)
 
 	u16 val = dsp_op_read_reg(sreg);
 	dsp_dmem_write(g_dsp.r[dreg], val);
-	g_dsp.r[sreg] = dsp_decrement_addr_reg(dreg);
+	g_dsp.r[dreg] = dsp_decrement_addr_reg(dreg);
 }
 
 // SRRI @$D, $S