4632 Commits

Author SHA1 Message Date
Ryan Houdek
bdca720e33 Fix some indention on AArch64 JIT. 2014-09-19 15:23:21 -05:00
Ryan Houdek
47e47891d4 [AArch64] Implement a bunch of integer instructions
16 new instructions for AArch64.
2014-09-19 15:23:21 -05:00
Ryan Houdek
5671530026 Merge pull request #1101 from FioraAeterna/fixfallbacks
JIT: simpler fallback conditions for load/store float
2014-09-19 15:23:01 -05:00
Ryan Houdek
5b4aa1d6d4 Merge pull request #1123 from FioraAeterna/eieio
JIT: change eieio and tlbsync to DoNothing
2014-09-19 15:19:41 -05:00
Ryan Houdek
7cc586d615 Merge pull request #1100 from FioraAeterna/psq_insts
JIT: implement remaining psq_l/st instruction variants
2014-09-19 15:16:44 -05:00
Fiora
0f53bba45a JIT: change eieio and tlbsync to DoNothing
The interpreter functions for these are no-ops anyways.
Also add some missing DoNothings to the ARM64 JIT.
2014-09-19 13:14:49 -07:00
Ryan Houdek
522d7eb275 Merge pull request #1109 from FioraAeterna/ps_cmp
JIT: add ps_cmp0/ps_cmp1/ps_res/ps_rsqrte
2014-09-19 14:41:05 -05:00
Ryan Houdek
526e92464b Merge pull request #1103 from FioraAeterna/floatconstnaming
JIT: rename a few constants to be more accurate
2014-09-19 13:21:06 -05:00
magumagu
32e5043b29 WIP XFB scaling.
Still an ugly mess.
2014-09-19 12:33:15 -05:00
Ryan Houdek
ec310811a8 Merge pull request #1114 from Sonicadvance1/AArch64-fix-build
Fix AArch64 JIT compiling.
2014-09-19 09:19:25 -05:00
Fiora
c130a496f2 JIT: fix fsel/ps_sel implementations for NaN input
fselx was the main problem, but ps_sel was wrong too (even if there were no
known reported bugs with it).

This fixes Beyond Good and Evil (at the least).
2014-09-19 01:58:13 -07:00
Fiora
d96016ed21 JIT: support byte-reversed stores/loads
4 more instructions down.

Store ones should be pretty well-tested; load ones seem to almost never be
used. I found them in Turok Evolution, so I was able to check code generation,
but the relevant code didn't seem to be called.
2014-09-18 20:38:44 -07:00
skidau
bd740ae9c7 Merge pull request #1111 from Tilka/fix_gcpad_setmotor
Fix GCPad::SetMotor()
2014-09-19 13:26:05 +10:00
Fiora
af8772700a JIT: add ps_res and ps_rsqrte using scalar implementations 2014-09-18 18:36:15 -07:00
Fiora
1b425dedd1 JIT: add ps_cmp0/ps_cmp1 implementations using current fcmp code 2014-09-18 17:57:28 -07:00
Ryan Houdek
a8abbdae85 Merge pull request #1106 from FioraAeterna/fixdebug2
JIT: fix debug mode
2014-09-18 19:52:35 -05:00
comex
3df935b98e Reset RSP after calling Jit in case it cleared the code cache. 2014-09-18 18:23:36 -04:00
Ryan Houdek
f709dda6aa Fix AArch64 JIT compiling. 2014-09-18 16:50:49 -05:00
Tillmann Karras
e35db54454 Fix and simplify GCPad::SetMotor()
abs() takes an int argument. Casting -0.5..0.5 to int always resulted in
zero.
2014-09-18 21:34:07 +02:00
Ryan Houdek
d54c8eb6bf Merge pull request #1098 from FioraAeterna/cvtsi2ss
JIT: use cvtsi2ss in paired singles
2014-09-18 06:51:37 -05:00
Ryan Houdek
0294b344e2 Merge pull request #1086 from FioraAeterna/fixsrawint
Interpreter: fix carry calculation in srawx
2014-09-18 06:41:37 -05:00
Fiora
cd7853bd50 JIT: fix debug mode 2014-09-18 03:14:04 -07:00
Fiora
9ab816e6e9 JIT: fix regression in ps_sel
My code didn't maintain correct semantics with floating-point NaNs (a < b is
not the same as "not a >= b" in float), which seems to have broken FIFA 12.
2014-09-17 21:43:44 -07:00
comex
217758b607 Correct inaccurate comment. 2014-09-17 22:30:33 -04:00
comex
6695b5acce Fix backwards #ifdef. 2014-09-17 22:30:20 -04:00
comex
97c9cb5882 Add missing push wrapper around UpdatePerformanceMonitor 2014-09-17 21:10:43 -04:00
Fiora
29fc151cc7 JIT: implement remaining psq_l/st instruction variants
These are used in at least a few popular games, including Super Smash Bros.
Brawl.
2014-09-17 17:10:27 -07:00
comex
7ad9027593 Be pedantic about stack overflow on Linux and OS X.
Add some magic to the fault handler to handle stack overflow due to BLR
optimization, and disable the optimization if fastmem is not enabled.
2014-09-17 20:08:09 -04:00
Fiora
cfd65c2762 JIT: rename a few constants to be more accurate
Remove the '2'; it's not longer applicable.
2014-09-17 16:59:35 -07:00
comex
755bd2c445 Reorganize backpatching a bit. Untested on ARM.
Rather than *MemTools.cpp checking whether the address is in the
emulated range itself (which, as of the next commit, doesn't cover every
kind of access the JIT might want to intercept) and doing PC
replacement, they just pass the access address and context to
jit->HandleFault, which does the rest itself.

Because SContext is now in JitInterface, I wanted JitBackpatch.h (which
defines it) to be lightweight, so I moved TrampolineCache and associated
x64{Analyzer,Emitter} dependencies into its own file.  I hate adding new
files in three places, two of which are MSVC...

While I'm at it, edit a misleading comment.
2014-09-17 19:57:06 -04:00
comex
7b0fdb52cd Run exception handlers on an alternate stack on Linux.
*Completely untested.*  Someone please test.
2014-09-17 19:57:04 -04:00
comex
bd4e75e69a Shorten the blr stub a bit. 2014-09-17 19:56:58 -04:00
comex
b597ec3e08 Opportunistically predict BLR destinations using RET.
When executing a BL-type instruction, push the new LR onto the stack,
then CALL the dispatcher or linked block rather than JMPing to it.  When
executing BLR, compare [rsp+8] to LR, and RET if it's right, which it
usually will be unless the thread was switched out.  If it's not right,
reset RSP to avoid overflow.

This both saves a trip through the dispatcher and improves branch
prediction.

There is a small possibility of stack overflow anyway, which should
be handled... *yawn*
2014-09-17 19:56:09 -04:00
comex
558dee84ca Wrap some function calls in ABI_Push|PopRegistersAndAdjustStack(0, 0);
These calls are made outside of JIT blocks, and thus previously did not
read any protection - register use is taken into account and the outer
dispatcher stack frame is sufficient.  However, if data is to be stored
on the stack, these calls must reserve stack shadow space on Windows to
avoid clobbering it.
2014-09-17 19:56:09 -04:00
Fiora
2a0b06f08c JIT: simpler fallback conditions for load/store float
I wasn't really thinking when I wrote these; d/s are for float registers, not
gprs.
2014-09-17 10:27:33 -07:00
Fiora
76c8bb40e8 JIT: update some rather outdated comments 2014-09-16 23:42:22 -07:00
Fiora
2ae6f13d22 JIT: use cvtsi2ss in paired singles
One less instruction for a few of the loads.
2014-09-16 22:50:33 -07:00
skidau
2c233c4976 Merge pull request #686 from FioraAeterna/fiora
JIT: Optimize JitAsmCommon, Float, and PS implementations
2014-09-17 14:06:14 +10:00
Rachel Bryk
5dc88a2673 Add hotkeys to select save state slots and to save/load the currently selected slots. 2014-09-16 19:19:41 -04:00
comex
7eea7080d9 Fix missing "return" 2014-09-16 00:25:21 -04:00
Fiora
764ce4b513 JIT: add fselx implementation
Based on a patch by Tilka.
2014-09-15 08:33:41 -07:00
Fiora
7ab820c6f8 JIT: Various JitAsmCommon optimizations
Use some SSE4 instructions in on CPUs that support them.
Use float instructions instead of int where appropriate (it's a cycle faster
on CPUs with arithmetic unit forwarding penalties).
2014-09-15 08:33:40 -07:00
Fiora
7b0f559ae1 JIT: various float optimizations 2014-09-15 08:33:40 -07:00
Fiora
34287b8042 JIT: some paired singles optimizations 2014-09-15 08:33:39 -07:00
Fiora
d02b7c7755 JIT: support immediate stores 2014-09-15 07:25:32 -07:00
Fiora
a248e49c97 Revert "Two small JIT optimizations" 2014-09-15 07:01:51 -07:00
Ryan Houdek
20af50b1c4 Merge pull request #1077 from FioraAeterna/integeropts2
Two small JIT optimizations
2014-09-15 07:09:11 -05:00
skidau
1458b59156 Merge pull request #1065 from Sonicadvance1/AArch64-fix-regcache
Fix all the current issues with the AArch64 register cache.
2014-09-15 13:02:16 +10:00
Fiora
3845c27155 JIT: save an instruction in psq_l 2014-09-14 15:12:57 -07:00
Fiora
af471d0a84 JIT: optimize andi(s)_rc
We usually don't need to do a sign-extend for the resulting flags.
2014-09-14 15:12:14 -07:00