Pokechu22 14119c86a4 DSPInterpreter: Fix IsLess ...

`IsLess` would incorrectly return true if both `SR_OVERFLOW` and `SR_SIGN` are set, as `(sr & SR_OVERFLOW) != (sr & SR_SIGN)` becomes `SR_OVERFLOW != SR_SIGN` which is true as the two masks are different.  This broke in e651592ef56521f6db71f8a671fe8c20b948d338.

This issue only affected the DSP LLE Interpreter, and not the DSP LLE JIT.

I've also included a simple test case for this.  `ax0.l` (on the top left) is set to 0 if the instruction following `IFL` does not execute and to 1 if it is executed.

2021-08-15 19:45:44 -07:00

..

accelerator_loop_test.ds

DSPSpy: Add a test for accelerator loop

2017-09-22 20:17:38 +02:00

accelerator_test.ds

DSPSpy: Add test for accelerator masking behaviour

2017-09-04 00:30:23 +02:00

andc_ls_test.ds

Hg:

2010-06-09 01:37:08 +00:00

arith_test.ds

Waiting for someone to run it:)

2009-06-29 20:31:41 +00:00

dr_test.ds

Meta:

2010-06-02 18:00:22 +00:00

dsp_base.inc

DSPSpy: save and restore $sr properly

2020-06-08 04:21:41 +01:00

dsp_test.ds

DSPSpy: save and restore $sr properly

2020-06-08 04:21:41 +01:00

ir_test.ds

Meta:

2010-06-02 18:00:22 +00:00

ld_test.ds

Meta:

2010-06-02 18:00:22 +00:00

less_test.ds

DSPInterpreter: Fix IsLess

2021-08-15 19:45:44 -07:00

mul_test.ds

Meta:

2010-06-02 18:00:22 +00:00

neg_test.ds

fixed neg and added arith test

2009-05-02 22:47:13 +00:00

op_test.ds

Hg:

2010-06-09 01:37:08 +00:00

unk_regs_test.ds

Meta:

2010-06-02 18:00:22 +00:00