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95ac48d605
There are a couple things in this PR. Fixes a bug where if we hit an invalid instruction we would infinite loop. Fixes an issue where on AArch64 it would show invalid instructions for all NEON instructions. This was due to asimd and crc being optional extensions and LLVM not enabling them by default. So we have to specify a CPU which has the feature. LLVM 3.6 will let us select by features instead of CPUs, but we don't have a release of that quite yet. If we are on an architecture that has a known instruction size, we will continue onward after hitting the invalid instruction. If we don't have a known instruction size like on x86, we will instead just dump the rest of the block.