JosJuice c04ef2eed3 JitArm64: Fix crandc/creqv/crorc setting eq bit
When I wrote 71e9766519, there was an interaction I didn't take into
account: When setting eq, SetCRFieldBit assumes that all bits in the
passed-in host register except the least significant bit are 0. But if
we use BIC/EON/ORN, all bits except the least significant bit get set to
1. This can cause eq to end up unset when it should be set.

This commit fixes the issue.

Note that in practice, we never have both bits_1_to_31_are_set and
negate at once, so while it looks like this commit adds an extra AND
instruction in some cases, those cases don't happen in practice, meaning
this fix shouldn't affect performance.
2025-01-06 10:03:27 +01:00
..