mirror of
https://github.com/dolphin-emu/dolphin.git
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0049ef3a2a
Rather than introduce this handling in every system instruction that modifies the FPSCR directly, we can instead just handle it within the data structure instead, which avoids duplicating mask handling across instructions. This also allows handling proper masking from the debugger register windows themselves without duplicating masking behavior there either.
866 lines
15 KiB
C++
866 lines
15 KiB
C++
// Copyright 2008 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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// Gekko related unions, structs, ...
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#pragma once
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#include "Common/BitField.h"
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#include "Common/CommonTypes.h"
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// --- Gekko Instruction ---
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union UGeckoInstruction
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{
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u32 hex = 0;
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UGeckoInstruction() = default;
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UGeckoInstruction(u32 hex_) : hex(hex_) {}
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struct
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{
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// Record bit
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// 1, if the condition register should be updated by this instruction
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u32 Rc : 1;
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u32 SUBOP10 : 10;
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// Source GPR
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u32 RB : 5;
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// Source or destination GPR
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u32 RA : 5;
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// Destination GPR
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u32 RD : 5;
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// Primary opcode
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u32 OPCD : 6;
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};
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struct
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{
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// Immediate, signed 16-bit
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signed SIMM_16 : 16;
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u32 : 5;
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// Conditions on which to trap
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u32 TO : 5;
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u32 OPCD_2 : 6;
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};
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struct
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{
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u32 Rc_2 : 1;
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u32 : 10;
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u32 : 5;
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u32 : 5;
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// Source GPR
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u32 RS : 5;
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u32 OPCD_3 : 6;
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};
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struct
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{
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// Immediate, unsigned 16-bit
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u32 UIMM : 16;
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u32 : 5;
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u32 : 5;
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u32 OPCD_4 : 6;
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};
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struct
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{
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// Link bit
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// 1, if branch instructions should put the address of the next instruction into the link
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// register
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u32 LK : 1;
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// Absolute address bit
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// 1, if the immediate field represents an absolute address
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u32 AA : 1;
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// Immediate, signed 24-bit
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u32 LI : 24;
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u32 OPCD_5 : 6;
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};
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struct
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{
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u32 LK_2 : 1;
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u32 AA_2 : 1;
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// Branch displacement, signed 14-bit (right-extended by 0b00)
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u32 BD : 14;
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// Branch condition
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u32 BI : 5;
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// Conditional branch control
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u32 BO : 5;
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u32 OPCD_6 : 6;
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};
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struct
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{
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u32 LK_3 : 1;
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u32 : 10;
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u32 : 5;
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u32 BI_2 : 5;
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u32 BO_2 : 5;
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u32 OPCD_7 : 6;
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};
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struct
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{
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u32 : 11;
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u32 RB_2 : 5;
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u32 RA_2 : 5;
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// ?
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u32 L : 1;
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u32 : 1;
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// Destination field in CR or FPSCR
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u32 CRFD : 3;
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u32 OPCD_8 : 6;
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};
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struct
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{
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signed SIMM_16_2 : 16;
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u32 RA_3 : 5;
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u32 L_2 : 1;
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u32 : 1;
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u32 CRFD_2 : 3;
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u32 OPCD_9 : 6;
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};
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struct
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{
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u32 UIMM_2 : 16;
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u32 RA_4 : 5;
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u32 L_3 : 1;
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u32 : 1;
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u32 CRFD_3 : 3;
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u32 OPCD_A : 6;
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};
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struct
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{
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u32 : 1;
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u32 SUBOP10_2 : 10;
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u32 RB_5 : 5;
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u32 RA_5 : 5;
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u32 L_4 : 1;
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u32 : 1;
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u32 CRFD_4 : 3;
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u32 OPCD_B : 6;
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};
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struct
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{
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u32 : 16;
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// Segment register
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u32 SR : 4;
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u32 : 1;
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u32 RS_2 : 5;
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u32 OPCD_C : 6;
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};
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// Table 59
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struct
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{
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u32 Rc_4 : 1;
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u32 SUBOP5 : 5;
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// ?
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u32 RC : 5;
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u32 : 5;
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u32 RA_6 : 5;
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u32 RD_2 : 5;
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u32 OPCD_D : 6;
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};
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struct
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{
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u32 : 10;
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// Overflow enable
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u32 OE : 1;
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// Special-purpose register
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u32 SPR : 10;
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u32 : 11;
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};
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struct
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{
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u32 : 10;
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u32 OE_3 : 1;
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// Upper special-purpose register
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u32 SPRU : 5;
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// Lower special-purpose register
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u32 SPRL : 5;
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u32 : 11;
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};
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// rlwinmx
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struct
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{
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u32 Rc_3 : 1;
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// Mask end
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u32 ME : 5;
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// Mask begin
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u32 MB : 5;
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// Shift amount
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u32 SH : 5;
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u32 : 16;
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};
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// crxor
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struct
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{
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u32 : 11;
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// Source bit in the CR
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u32 CRBB : 5;
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// Source bit in the CR
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u32 CRBA : 5;
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// Destination bit in the CR
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u32 CRBD : 5;
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u32 : 6;
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};
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// mftb
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struct
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{
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u32 : 11;
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// Time base register
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u32 TBR : 10;
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u32 : 11;
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};
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struct
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{
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u32 : 11;
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// Upper time base register
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u32 TBRU : 5;
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// Lower time base register
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u32 TBRL : 5;
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u32 : 11;
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};
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struct
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{
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u32 : 18;
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// Source field in the CR or FPSCR
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u32 CRFS : 3;
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u32 : 2;
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u32 CRFD_5 : 3;
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u32 : 6;
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};
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struct
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{
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u32 : 12;
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// Field mask, identifies the CR fields to be updated by mtcrf
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u32 CRM : 8;
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u32 : 1;
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// Destination FPR
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u32 FD : 5;
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u32 : 6;
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};
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struct
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{
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u32 : 6;
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// Source FPR
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u32 FC : 5;
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// Source FPR
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u32 FB : 5;
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// Source FPR
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u32 FA : 5;
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// Source FPR
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u32 FS : 5;
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u32 : 6;
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};
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struct
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{
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u32 : 17;
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// Field mask, identifies the FPSCR fields to be updated by mtfsf
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u32 FM : 8;
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u32 : 7;
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};
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// paired single quantized load/store
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struct
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{
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u32 : 1;
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u32 SUBOP6 : 6;
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// Graphics quantization register to use
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u32 Ix : 3;
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// 0: paired single, 1: scalar
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u32 Wx : 1;
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u32 : 1;
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// Graphics quantization register to use
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u32 I : 3;
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// 0: paired single, 1: scalar
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u32 W : 1;
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u32 : 16;
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};
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struct
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{
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signed SIMM_12 : 12;
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u32 : 20;
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};
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struct
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{
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u32 : 11;
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// Number of bytes to use in lswi/stswi (0 means 32 bytes)
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u32 NB : 5;
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};
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};
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//
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// --- Gekko Special Registers ---
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//
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// quantize types
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enum EQuantizeType : u32
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{
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QUANTIZE_FLOAT = 0,
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QUANTIZE_INVALID1 = 1,
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QUANTIZE_INVALID2 = 2,
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QUANTIZE_INVALID3 = 3,
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QUANTIZE_U8 = 4,
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QUANTIZE_U16 = 5,
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QUANTIZE_S8 = 6,
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QUANTIZE_S16 = 7,
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};
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// GQR Register
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union UGQR
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{
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BitField<0, 3, EQuantizeType> st_type;
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BitField<8, 6, u32> st_scale;
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BitField<16, 3, EQuantizeType> ld_type;
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BitField<24, 6, u32> ld_scale;
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u32 Hex = 0;
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UGQR() = default;
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explicit UGQR(u32 hex_) : Hex{hex_} {}
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};
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#define XER_CA_SHIFT 29
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#define XER_OV_SHIFT 30
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#define XER_SO_SHIFT 31
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#define XER_OV_MASK 1
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#define XER_SO_MASK 2
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// XER
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union UReg_XER
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{
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struct
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{
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u32 BYTE_COUNT : 7;
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u32 : 1;
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u32 BYTE_CMP : 8;
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u32 : 13;
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u32 CA : 1;
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u32 OV : 1;
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u32 SO : 1;
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};
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u32 Hex = 0;
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UReg_XER() = default;
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explicit UReg_XER(u32 hex_) : Hex{hex_} {}
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};
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// Machine State Register
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union UReg_MSR
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{
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struct
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{
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u32 LE : 1;
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u32 RI : 1;
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u32 PM : 1;
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u32 : 1; // res28
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u32 DR : 1;
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u32 IR : 1;
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u32 IP : 1;
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u32 : 1; // res24
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u32 FE1 : 1;
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u32 BE : 1;
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u32 SE : 1;
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u32 FE0 : 1;
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u32 MCHECK : 1;
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u32 FP : 1;
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u32 PR : 1;
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u32 EE : 1;
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u32 ILE : 1;
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u32 : 1; // res14
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u32 POW : 1;
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u32 res : 13;
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};
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u32 Hex = 0;
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UReg_MSR() = default;
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explicit UReg_MSR(u32 hex_) : Hex{hex_} {}
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};
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#define FPRF_SHIFT 12
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#define FPRF_MASK (0x1F << FPRF_SHIFT)
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// FPSCR exception flags
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enum FPSCRExceptionFlag : u32
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{
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FPSCR_FX = 1U << (31 - 0),
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FPSCR_FEX = 1U << (31 - 1),
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FPSCR_VX = 1U << (31 - 2),
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FPSCR_OX = 1U << (31 - 3),
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FPSCR_UX = 1U << (31 - 4),
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FPSCR_ZX = 1U << (31 - 5),
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FPSCR_XX = 1U << (31 - 6),
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FPSCR_VXSNAN = 1U << (31 - 7),
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FPSCR_VXISI = 1U << (31 - 8),
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FPSCR_VXIDI = 1U << (31 - 9),
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FPSCR_VXZDZ = 1U << (31 - 10),
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FPSCR_VXIMZ = 1U << (31 - 11),
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FPSCR_VXVC = 1U << (31 - 12),
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FPSCR_VXSOFT = 1U << (31 - 21),
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FPSCR_VXSQRT = 1U << (31 - 22),
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FPSCR_VXCVI = 1U << (31 - 23),
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FPSCR_VE = 1U << (31 - 24),
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FPSCR_VX_ANY = FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI | FPSCR_VXZDZ | FPSCR_VXIMZ | FPSCR_VXVC |
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FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI,
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FPSCR_ANY_X = FPSCR_OX | FPSCR_UX | FPSCR_ZX | FPSCR_XX | FPSCR_VX_ANY,
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};
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// Floating Point Status and Control Register
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union UReg_FPSCR
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{
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struct
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{
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// Rounding mode (towards: nearest, zero, +inf, -inf)
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u32 RN : 2;
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// Non-IEEE mode enable (aka flush-to-zero)
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u32 NI : 1;
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// Inexact exception enable
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u32 XE : 1;
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// IEEE division by zero exception enable
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u32 ZE : 1;
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// IEEE underflow exception enable
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u32 UE : 1;
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// IEEE overflow exception enable
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u32 OE : 1;
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// Invalid operation exception enable
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u32 VE : 1;
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// Invalid operation exception for integer conversion (sticky)
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u32 VXCVI : 1;
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// Invalid operation exception for square root (sticky)
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u32 VXSQRT : 1;
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// Invalid operation exception for software request (sticky)
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u32 VXSOFT : 1;
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// reserved
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u32 : 1;
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// Floating point result flags (includes FPCC) (not sticky)
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// from more to less significand: class, <, >, =, ?
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u32 FPRF : 5;
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// Fraction inexact (not sticky)
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u32 FI : 1;
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// Fraction rounded (not sticky)
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u32 FR : 1;
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// Invalid operation exception for invalid comparison (sticky)
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u32 VXVC : 1;
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// Invalid operation exception for inf * 0 (sticky)
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u32 VXIMZ : 1;
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// Invalid operation exception for 0 / 0 (sticky)
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u32 VXZDZ : 1;
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// Invalid operation exception for inf / inf (sticky)
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u32 VXIDI : 1;
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// Invalid operation exception for inf - inf (sticky)
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u32 VXISI : 1;
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// Invalid operation exception for SNaN (sticky)
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u32 VXSNAN : 1;
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// Inexact exception (sticky)
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u32 XX : 1;
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// Division by zero exception (sticky)
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u32 ZX : 1;
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// Underflow exception (sticky)
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u32 UX : 1;
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// Overflow exception (sticky)
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u32 OX : 1;
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// Invalid operation exception summary (not sticky)
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u32 VX : 1;
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// Enabled exception summary (not sticky)
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u32 FEX : 1;
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// Exception summary (sticky)
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u32 FX : 1;
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};
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u32 Hex = 0;
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// The FPSCR's 20th bit (11th from a little endian perspective)
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// is defined as reserved and set to zero. Attempts to modify it
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// are ignored by hardware, so we do the same.
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static constexpr u32 mask = 0xFFFFF7FF;
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UReg_FPSCR() = default;
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explicit UReg_FPSCR(u32 hex_) : Hex{hex_ & mask} {}
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UReg_FPSCR& operator=(u32 value)
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{
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Hex = value & mask;
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return *this;
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}
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UReg_FPSCR& operator|=(u32 value)
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{
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Hex |= value & mask;
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return *this;
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}
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UReg_FPSCR& operator&=(u32 value)
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{
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Hex &= value;
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return *this;
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}
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UReg_FPSCR& operator^=(u32 value)
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{
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Hex ^= value & mask;
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return *this;
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}
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void ClearFIFR()
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{
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FI = 0;
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FR = 0;
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}
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};
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// Hardware Implementation-Dependent Register 0
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union UReg_HID0
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{
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struct
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{
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u32 NOOPTI : 1;
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u32 : 1;
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u32 BHT : 1;
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u32 ABE : 1;
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u32 : 1;
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u32 BTIC : 1;
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u32 DCFA : 1;
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u32 SGE : 1;
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u32 IFEM : 1;
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u32 SPD : 1;
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u32 DCFI : 1;
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u32 ICFI : 1;
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u32 DLOCK : 1;
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u32 ILOCK : 1;
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u32 DCE : 1;
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u32 ICE : 1;
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u32 NHR : 1;
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u32 : 3;
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u32 DPM : 1;
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u32 SLEEP : 1;
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u32 NAP : 1;
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u32 DOZE : 1;
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u32 PAR : 1;
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u32 ECLK : 1;
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u32 : 1;
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u32 BCLK : 1;
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u32 EBD : 1;
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u32 EBA : 1;
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u32 DBP : 1;
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u32 EMCP : 1;
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};
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u32 Hex = 0;
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};
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// Hardware Implementation-Dependent Register 2
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union UReg_HID2
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{
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struct
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{
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u32 : 16;
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u32 DQOEE : 1;
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u32 DCMEE : 1;
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u32 DNCEE : 1;
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u32 DCHEE : 1;
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u32 DQOERR : 1;
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u32 DCMERR : 1;
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u32 DNCERR : 1;
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u32 DCHERR : 1;
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u32 DMAQL : 4;
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u32 LCE : 1;
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u32 PSE : 1;
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u32 WPE : 1;
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u32 LSQE : 1;
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};
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u32 Hex = 0;
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UReg_HID2() = default;
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explicit UReg_HID2(u32 hex_) : Hex{hex_} {}
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};
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// Hardware Implementation-Dependent Register 4
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union UReg_HID4
|
|
{
|
|
struct
|
|
{
|
|
u32 : 20;
|
|
u32 L2CFI : 1;
|
|
u32 L2MUM : 1;
|
|
u32 DBP : 1;
|
|
u32 LPE : 1;
|
|
u32 ST0 : 1;
|
|
u32 SBE : 1;
|
|
u32 : 1;
|
|
u32 BPD : 2;
|
|
u32 L2FM : 2;
|
|
u32 : 1;
|
|
};
|
|
u32 Hex = 0;
|
|
|
|
UReg_HID4() = default;
|
|
explicit UReg_HID4(u32 hex_) : Hex{hex_} {}
|
|
};
|
|
|
|
// SPR1 - Page Table format
|
|
union UReg_SPR1
|
|
{
|
|
u32 Hex;
|
|
struct
|
|
{
|
|
u32 htaborg : 16;
|
|
u32 : 7;
|
|
u32 htabmask : 9;
|
|
};
|
|
};
|
|
|
|
// MMCR0 - Monitor Mode Control Register 0 format
|
|
union UReg_MMCR0
|
|
{
|
|
u32 Hex;
|
|
struct
|
|
{
|
|
u32 PMC2SELECT : 6;
|
|
u32 PMC1SELECT : 7;
|
|
u32 PMCTRIGGER : 1;
|
|
u32 PMCINTCONTROL : 1;
|
|
u32 PMC1INTCONTROL : 1;
|
|
u32 THRESHOLD : 6;
|
|
u32 INTONBITTRANS : 1;
|
|
u32 RTCSELECT : 2;
|
|
u32 DISCOUNT : 1;
|
|
u32 ENINT : 1;
|
|
u32 DMR : 1;
|
|
u32 DMS : 1;
|
|
u32 DU : 1;
|
|
u32 DP : 1;
|
|
u32 DIS : 1;
|
|
};
|
|
};
|
|
|
|
// MMCR1 - Monitor Mode Control Register 1 format
|
|
union UReg_MMCR1
|
|
{
|
|
u32 Hex;
|
|
struct
|
|
{
|
|
u32 : 22;
|
|
u32 PMC4SELECT : 5;
|
|
u32 PMC3SELECT : 5;
|
|
};
|
|
};
|
|
|
|
// Write Pipe Address Register
|
|
union UReg_WPAR
|
|
{
|
|
struct
|
|
{
|
|
u32 BNE : 1;
|
|
u32 : 4;
|
|
u32 GB_ADDR : 27;
|
|
};
|
|
u32 Hex = 0;
|
|
|
|
UReg_WPAR() = default;
|
|
explicit UReg_WPAR(u32 hex_) : Hex{hex_} {}
|
|
};
|
|
|
|
// Direct Memory Access Upper register
|
|
union UReg_DMAU
|
|
{
|
|
struct
|
|
{
|
|
u32 DMA_LEN_U : 5;
|
|
u32 MEM_ADDR : 27;
|
|
};
|
|
u32 Hex = 0;
|
|
|
|
UReg_DMAU() = default;
|
|
explicit UReg_DMAU(u32 hex_) : Hex{hex_} {}
|
|
};
|
|
|
|
// Direct Memory Access Lower (DMAL) register
|
|
union UReg_DMAL
|
|
{
|
|
struct
|
|
{
|
|
u32 DMA_F : 1;
|
|
u32 DMA_T : 1;
|
|
u32 DMA_LEN_L : 2;
|
|
u32 DMA_LD : 1;
|
|
u32 LC_ADDR : 27;
|
|
};
|
|
u32 Hex = 0;
|
|
|
|
UReg_DMAL() = default;
|
|
explicit UReg_DMAL(u32 hex_) : Hex{hex_} {}
|
|
};
|
|
|
|
union UReg_BAT_Up
|
|
{
|
|
struct
|
|
{
|
|
u32 VP : 1;
|
|
u32 VS : 1;
|
|
u32 BL : 11; // Block length (aka block size mask)
|
|
u32 : 4;
|
|
u32 BEPI : 15;
|
|
};
|
|
u32 Hex = 0;
|
|
|
|
UReg_BAT_Up() = default;
|
|
explicit UReg_BAT_Up(u32 hex_) : Hex{hex_} {}
|
|
};
|
|
|
|
union UReg_BAT_Lo
|
|
{
|
|
struct
|
|
{
|
|
u32 PP : 2;
|
|
u32 : 1;
|
|
u32 WIMG : 4;
|
|
u32 : 10;
|
|
u32 BRPN : 15; // Physical Block Number
|
|
};
|
|
u32 Hex = 0;
|
|
|
|
UReg_BAT_Lo() = default;
|
|
explicit UReg_BAT_Lo(u32 hex_) : Hex{hex_} {}
|
|
};
|
|
|
|
union UReg_PTE
|
|
{
|
|
struct
|
|
{
|
|
u64 API : 6;
|
|
u64 H : 1;
|
|
u64 VSID : 24;
|
|
u64 V : 1;
|
|
u64 PP : 2;
|
|
u64 : 1;
|
|
u64 WIMG : 4;
|
|
u64 C : 1;
|
|
u64 R : 1;
|
|
u64 : 3;
|
|
u64 RPN : 20;
|
|
};
|
|
|
|
u64 Hex = 0;
|
|
u32 Hex32[2];
|
|
};
|
|
|
|
//
|
|
// --- Gekko Types and Defs ---
|
|
//
|
|
|
|
// branches
|
|
enum
|
|
{
|
|
BO_BRANCH_IF_CTR_0 = 2, // 3
|
|
BO_DONT_DECREMENT_FLAG = 4, // 2
|
|
BO_BRANCH_IF_TRUE = 8, // 1
|
|
BO_DONT_CHECK_CONDITION = 16, // 0
|
|
};
|
|
|
|
// Special purpose register indices
|
|
enum
|
|
{
|
|
SPR_XER = 1,
|
|
SPR_LR = 8,
|
|
SPR_CTR = 9,
|
|
SPR_DSISR = 18,
|
|
SPR_DAR = 19,
|
|
SPR_DEC = 22,
|
|
SPR_SDR = 25,
|
|
SPR_SRR0 = 26,
|
|
SPR_SRR1 = 27,
|
|
SPR_TL = 268,
|
|
SPR_TU = 269,
|
|
SPR_TL_W = 284,
|
|
SPR_TU_W = 285,
|
|
SPR_PVR = 287,
|
|
SPR_SPRG0 = 272,
|
|
SPR_SPRG1 = 273,
|
|
SPR_SPRG2 = 274,
|
|
SPR_SPRG3 = 275,
|
|
SPR_EAR = 282,
|
|
SPR_IBAT0U = 528,
|
|
SPR_IBAT0L = 529,
|
|
SPR_IBAT1U = 530,
|
|
SPR_IBAT1L = 531,
|
|
SPR_IBAT2U = 532,
|
|
SPR_IBAT2L = 533,
|
|
SPR_IBAT3U = 534,
|
|
SPR_IBAT3L = 535,
|
|
SPR_DBAT0U = 536,
|
|
SPR_DBAT0L = 537,
|
|
SPR_DBAT1U = 538,
|
|
SPR_DBAT1L = 539,
|
|
SPR_DBAT2U = 540,
|
|
SPR_DBAT2L = 541,
|
|
SPR_DBAT3U = 542,
|
|
SPR_DBAT3L = 543,
|
|
SPR_IBAT4U = 560,
|
|
SPR_IBAT4L = 561,
|
|
SPR_IBAT5U = 562,
|
|
SPR_IBAT5L = 563,
|
|
SPR_IBAT6U = 564,
|
|
SPR_IBAT6L = 565,
|
|
SPR_IBAT7U = 566,
|
|
SPR_IBAT7L = 567,
|
|
SPR_DBAT4U = 568,
|
|
SPR_DBAT4L = 569,
|
|
SPR_DBAT5U = 570,
|
|
SPR_DBAT5L = 571,
|
|
SPR_DBAT6U = 572,
|
|
SPR_DBAT6L = 573,
|
|
SPR_DBAT7U = 574,
|
|
SPR_DBAT7L = 575,
|
|
SPR_GQR0 = 912,
|
|
SPR_HID0 = 1008,
|
|
SPR_HID1 = 1009,
|
|
SPR_HID2 = 920,
|
|
SPR_HID4 = 1011,
|
|
SPR_WPAR = 921,
|
|
SPR_DMAU = 922,
|
|
SPR_DMAL = 923,
|
|
SPR_ECID_U = 924,
|
|
SPR_ECID_M = 925,
|
|
SPR_ECID_L = 926,
|
|
SPR_L2CR = 1017,
|
|
|
|
SPR_UMMCR0 = 936,
|
|
SPR_MMCR0 = 952,
|
|
SPR_PMC1 = 953,
|
|
SPR_PMC2 = 954,
|
|
|
|
SPR_UMMCR1 = 940,
|
|
SPR_MMCR1 = 956,
|
|
SPR_PMC3 = 957,
|
|
SPR_PMC4 = 958,
|
|
};
|
|
|
|
// Exceptions
|
|
enum
|
|
{
|
|
EXCEPTION_DECREMENTER = 0x00000001,
|
|
EXCEPTION_SYSCALL = 0x00000002,
|
|
EXCEPTION_EXTERNAL_INT = 0x00000004,
|
|
EXCEPTION_DSI = 0x00000008,
|
|
EXCEPTION_ISI = 0x00000010,
|
|
EXCEPTION_ALIGNMENT = 0x00000020,
|
|
EXCEPTION_FPU_UNAVAILABLE = 0x00000040,
|
|
EXCEPTION_PROGRAM = 0x00000080,
|
|
EXCEPTION_PERFORMANCE_MONITOR = 0x00000100,
|
|
|
|
EXCEPTION_FAKE_MEMCHECK_HIT = 0x00000200,
|
|
};
|
|
|
|
constexpr s32 SignExt16(s16 x)
|
|
{
|
|
return (s32)x;
|
|
}
|
|
constexpr s32 SignExt26(u32 x)
|
|
{
|
|
return x & 0x2000000 ? (s32)(x | 0xFC000000) : (s32)(x);
|
|
}
|